flexio 配置为8080总线 WR引脚异常

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flexio 配置为8080总线 WR引脚异常

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tim-wei
Contributor I

根据 AN12822 在IMRT1011中使用flexio仿真8080端口,在数据传输过程中 WR引脚在WR 写入数据的过程中发生一个脉冲,WR低电平20ns后发生一个时长10ns脉冲 整个低电平应该是50ns才对,这个脉冲是偶然发生的的不是每个写入的时候都会有

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jeremyzhou
NXP Employee
NXP Employee

Hi,

非常感谢使用NXP产品,很高兴为你提供技术支持!
为方便分析,请问是否有找到复现此现象的步骤。

Have a great day,
TIC

 

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tim-wei
Contributor I

在使用读取的时候这个现象很明显

FLEXIO_MCULCD_StartTransfer(base);
FLEXIO_MCULCD_WriteCommandBlocking(base, 0xD3);
FLEXIO_MCULCD_ReadDataArrayBlocking(base, commandParam, 4U);
FLEXIO_MCULCD_StopTransfer(base);
HX8357_Delay(2000);

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jeremyzhou
NXP Employee
NXP Employee

Hi ,

我运行附件代码,验证了一下,并未发现你说的现象。

还有你说的现象是否影响代码的功能和运行结果。

Have a great day,
TIC

 

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tim-wei
Contributor I

显示是正常的 就是逻辑风险仪看着有点问题。谢谢了

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