clock configuration for SPE PHY and RT1064

[frankk]

Hello,

I would like to connect a single pair ethernet PHY (RMII) to RT1064. There are two modes for the PHY, master and slave mode.

In slave mode the PHY receives a 50MHz reference signal on its crystal input Xi pin. For this I would use ENET1_TX_CLK pin as 50MHz output clock derived from ref_enetpll. I think this is clear.

In PHY master mode the PHY outputs a 50MHz reference clock and it needs additonally a 25MHz crystal clock on its Xi pin. For this I would connect the 50MHz PHY reference clock to ENET1_REF_CLK. And to save the crystal I would leave the ENET1_TX_CLK connection to Xi pin of the PHY.

In that point I would say the RT1064 reference manual is not precise. Is it possible to use input ENET1_REF_CLK as the module reference clock and simultaneously a 25MHz ENET1_TX_CLK derived from ref_enetpll?

Any advice would be appreciated.

Regards,

Frank

[jeremyzhou]

Hi ,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
To be prudent, whether you share the block diagram of your design, as it can prevent me from misunderstanding your question.
Looking forward to your reply.

Have a great day,
TIC

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[frankk]

Hi,

please find below the block diagram. I hope this will make it more clear

Regards,

Frank

[jeremyzhou]

Hi,

Thanks for your reply.
1) Is this configuration possible?
-- No, I'm afraid not. For slave mode, the PHY device receives the reference clock from the ENET_REF_CLK pin.
For master mode, the ENET_REF_CLK pin receives the external clock as the clock source, the PHY device needs an external OSC to provide the clock.

Have a great day,
TIC

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[frankk]

Hi,

thank you very much for your reply and help. Ok now I have one more question because the reference manual is not clear in that point.

For me now the slave mode is more important.

jeremyzhou schrieb:

Hi,

Thanks for your reply.
1) Is this configuration possible?
-- No, I'm afraid not. For slave mode, the PHY device receives the reference clock from the ENET_REF_CLK pin.
For master mode, ...

1) How can I use ENET_REF_CLK pin as an output? On page 2096 this signal is noted as an input.

2) Also the sentence "This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function." is not clear to me.

What clock is meant by "This clock.." ?

Thanks in advance for your help.

Have a great day,

Frank

[jeremyzhou]

Hi,

Thanks for your reply.

1) How can I use the ENET_REF_CLK pin as an output? On page 2096 this signal is noted as an input.
-- Yes, when working in RMII mode, the ENET_REF_CLK should receive an external clock, for the RT series, it supports to use the ref_enetpll as the clock source of both the ENET_REF_CLK and PHY device.
And the ref_enetpll output clock to the PHY device via the ENET_REF_CLK pin.

Have a great day,
TIC

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