Wait mode doesn't seem to work

[Ahlan]

I am using an MCIMXRT1052 processor and seem to be having a problem understanding the wait mode.

I use a GPT timer and the Wdog3 and have configured both of these to be disabled in wait mode.

I am therefore surprised that the GPT timer still counts whilst the processor is executing the WFI instruction.

Moreover the watchdog can go off whilst processing the WFI instruction.

My understanding is that executing the WFI instruction places the processor into Idle mode until the next interrupt.

And that if the least significant 2 bits of CLPCR are 01 then Idle will transfer to Wait mode.
CLPCR defaults to 79H - I have checked this.
So why don't we go into WAIT mode?

Or if we do why does the GPT and Watchdog still count?

Do I have to configure low power gating (CG12 in CCM_CCGR0)?

I tried this but it didn't seem to help.

I guess I am misunderstanding a concept or not configuring the processor correctly.

So any clues, suggestions & ideas are all very welcome.

[Ahlan]

Hi,

To answer my own question for the benefit of anyone interested, it seems that the problem wasn't with my understanding nor with my programming but with a bug in the silicon of the MCIMXRT1052 processors we were using. The same code that failed to work as expected on the 1052 works, without change, on the new evaluation boards we are using that are based on the MCIMXRT1062 processor.  

[Ahlan]

This question is flagged "assumed answered" however it isn't - how can I change the status of the question?

Anyway - the problem still remains.

I issue a WFI and spend a considerable % of my time there during which power consumption is reduced.

So this shows that the WFI instruction is doing something.

However my GPT counters continue to count despite being disabled in wait mode.

Therefore I am not in wait mode.

I naively assumed that I would enter wait mode when i issued the WFI instruction, but this seems not to be the case.

So there must be something that enables the transition from the mode WFI enters (Idle?) to Wait mode.

CLCPR seems to be setup correctly but is there something else that needs to be done?

Has nobody else tried this?

Perhaps its a fault in the silicon?

Setup two GPT counters identically except one is disabled during wait and the other not.

Issue a WFI.

The timers should be different after the WFI.

But mine aren't.

what could I be doing wrong?

Best wishes,

Ahlan

[igorpadykov]

Hi Ahlan

>However my GPT counters continue to count despite being disabled in wait mode.

in addition for checking that register GPTx_CR, bit WAITEN=0 GPT- is disabled in wait mode,

one can consider erratum ERR007265 CCM: When improper low-power sequence.. i.MX RT1050 Errata
https://www.nxp.com/docs/en/errata/IMXRT1050CE.pdf

Alternatively check clock source, selected by  GPTx_CR[CLKSRC] is disabled in
wait mode with CCM Clock Gating Registers (CCM_CCGRn).

To check if clock was stopped in wait mode one can output it on CLKO1,2 and check it
with oscillosope, use sect.18.7.19 CCM Clock Output Source Register (CCM_CCOSR)
Reference Manual.

Best regards
igor

[Ahlan]

I have just measured the power consumption and have determined that it is 30% lower when we use the WFI instruction within a loop in the background task as opposed to the same loop without the WFI instruction.

So it seems that WFI is placing the processor into some form of low power mode - just not into the WAIT mode that can be used to selectively disable specific modules. For example GPT2 - why doesn't this count differently to GPT1 when programmed identically except that GPT2 is (supposed to be) disabled in WAIT mode?

Best wishes,

Ahlan

[igorpadykov]

reason may be that wdog some bits are once time written, as described in

sect.58.7.1.2.2 Function Watchdog Control Register (WDOGx_WCR) i.MX6RT Reference Manual

WDZST, WDBG and WDW are write-once only bits. Once the software does a write
access to these bits, they will be locked and cannot be reprogrammed until the next
system reset assertion.

~igor

[igorpadykov]

Hi Ahlan

one can look at AN12085 How to use iMXRT Low Power feature

https://www.nxp.com/docs/en/application-note/AN12085.pdf 

EVK-MIMXRT1050 SDK gpt example in sdk/boards/evkbimxrt1050/driver_examples/gpt/timer/gpt_timer.c

Welcome | MCUXpresso SDK Builder 

Much easier to test STOP mode as it stops all clocks (CPU, system buses and all PLLs).

For example check ahb_clk_root on CLKO1 (setting CLKO1_SEL, CCM_CCOSR).
GPIO_SD_B0_04 (ALT6) Table 4-1. Muxing Options, use sect.18.7.19 CCM Clock Output Source

Register (CCM_CCOSR). PLL1 --> AHB_CLK_ROOT Figure 18-5. BUS clock generation,
sect.18.6.3.3.1 Entering STOP mode i.MX RT1050 Reference Manual.

https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf

Best regards
igor

[Ahlan]

Dear Igor,

When I wrote that I have experimented with CCM I meant that I had tried exactly what you have suggested. Setting the clock gates off in Wait state made no difference - hence my conclusion that the processor is not entering wait state.

I am using an evaluation board with bare board software that we have entirely written ourselves.

Using a GPT timer I can measure how much time is spent between immediately before and immediately after the WFI and therefore know that the WFI instruction is behaving as expected except that the processor isn't going into wait mode as far as GPT and Wdog3 are concerned. I haven't measured power consumption but it wouldn't surprise me if the power usage was the same as if I had used a loop instead of the WFI..

I guess that entering low power modes needs to be enabled. I have seen and checked CLCPR but I wonder if there is something else that needs to be done.

We are booting into on-chip flash so the boot fuses could be setting something that disables low power mode in much the same way that the watchdog is disabled.

Best regards,

Ahlan

[Ahlan]

Dear Igor,

Thank you for your reply.

I set Waiten (bit 3) in GPT2_CR and cleared it in GPT1_CR but otherwise use the counters the same. I expected GPT2 to count less than GPT1 to reflect the amount of time spent executing WFI. I have measured the time spent executing the WFI and see that my program spends about 98.5% of its time executing WFI however GPT2 has the same count as GPT1.

I have a similar problem with the Watchdog. I leave the Wait (bit 1) clear in Wdog3_Cs (400B_C000) to disable the watchdog whilst in Wait - yet the watchdog goes off whilst I am executing the WFI.

Note I am using Wdog3 as described in Chapter 59 and use Revision 1 of the reference manual dated 03/2018

These symptoms suggest that although I am executing the WFI instruction I am not entering Wait mode.

I see that it is possible to decouple this using CLCPR but have checked that this is still 0x79 and therefore the WFI instruction should place the processor in wait mode - but I don't think it does.

I have experimented with CCM but the same thing happens. The gating does not change when I execute WFI.

Any ideas why not?

Best wishes,

Ahlan

[igorpadykov]

Hi Ahlan

also may be useful to check sect.18.7.21 CCM Clock Gating Register 0 (CCM_CCGR0)

i.MX RT1050 Reference Manual for settings CGR value = 01

"Clock is on in run mode, but off in WAIT and STOP modes"
https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf

Regarding"These symptoms suggest that although I am executing the WFI instruction I am not entering Wait mode."

is it entering wait mode without gpt/wdog, as there may be other pending interrupts.

What software and board used in the case.

Best regards
igor

[igorpadykov]

Hi Ahlan

there are special bits for controlling behavior wdt, gpt in low power

modes: bit WAITEN described in sect.33.6.1 GPT Control Register GPTx_CR,

WDZST in WDOG_WCR sect.58.7.1.2.4 Fields i.MX RT1050 Reference Manual (rev.0  10/2017)
https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf

Best regards
igor
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