Ste up clock source on EVK-MIMXRT1064

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Ste up clock source on EVK-MIMXRT1064

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max_yang1
Contributor III

Reference:

Board: EVK-MIMXRT1064 SDK example: lpspi_polling_b2b_transfer

 

Where I can find a general guide on setting clock source, for this case, LPSPI, for example. On section 48.3.6 of reference manual, there is really no specifics how to set them, and chich one needs to be set, or which is derived from root clock.

If I open Expresso, clock diagram for the board

I can see output of LPSPI is derived from USB1PLL3, outputs  105.6 MHz, this line was generated.

#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL

 

However, in the quoted example, 

#define LPSPI_MASTER_CLK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER + 1U))

EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER=7

When I ran this example, this gives 60MHz.

Is there a guide to selection source, and how do I know what pre-scale should be for that source? What is the good frequency range LPSPI could accept?

Thanks in advance,

 

Max

 

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max_yang1
Contributor III

Mark and Edwin,

Thanks for the links to the documents. I think they make sense. My question is more at SDK software side: if I look at clock_config.* file, they look more like what I can see from these documents. However the quoted example, does not appear to use what is already in clock_config.* file. More over when I debug though fsl_lpspi.c,  the call to LPSPI_MasterSetBaudRate() does not really do anything but always returned from line 508.

There is only one statement in RM about clock in  48.3.6

"Bus clock The bus clock is only used for bus accesses to the LPSPI control and configuration registers. The
bus clock frequency must be high enough to support the data bandwidth requirements of the LPSPI
registers, including the FIFOs."

There is also a functional clock in the module, how is that related to the frequecy?

Max

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi again @max_yang1,

The "return 0" of line 508 of the LPSPI_MasterSetBaudRate() routine is a mechanism to ensure that the RT is indeed set up as a Master, as well as making sure that the LPSPI module is disabled. The Baudrate cannot be changed while the LPSPI module is enabled, so if your RT is a master device, disable the SPI module and try again.

Regarding your other question about the module's functional clock, this is what enables the module to work. Without the functional clock, the whole module is basically off. Also, it provides a time base for the module's baud rate. SCLK is derived from the functional clock by setting a prescale value to the functional clock, and that way output the SCLK. This means that SCLK cannot be greater than the module's clk.

BR,
Edwin.

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mjbcswitzerland
Specialist V

Hi

See Section 1.8 of https://www.utasker.com/docs/iMX/i.MX_RT_1021_uTasker.pdf (valid also for 1064)
for a practical overview of the possible clock sources and settings.

Regards

Mark

 

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @max_yang1,

When setting up the clock configuration, we recommend our clients to look into the "14.4 CCM Clock Tree" section of the RM, since it provides a visual representation of the routing for each clock output. This way, it is easy to see the according registers for each clock root. In this case, for the LPSPI module:

EdwinHz_1-1690487956222.png

We can see the LPSPI's clock root depends on the LPSPI_CLK_SEL bitfield for selecting the clock source, as well as the LPSPI_PODF for the dividing factor for said clock source. Both of these bit fields are located on the CCM_CBCMR register:

EdwinHz_2-1690488123306.png

EdwinHz_3-1690488224110.png

You would go about the same process for any clock root you wish to modify.

I recommend you to look at the following community article: https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/RT-s-System-Clocks/ta-p/1151118. It describes in more detail how the RT set's up it's clocks, and how to do this in ConfigTools, which is a more user-friendly way of adjusting the clocks visually, rather than manually on code. ConfigTools is a great way of adjusting the clocks as well, since it ensures that you don't go over the maximum clock speeds, or under the minimum clock speeds for each clock source. Besides this, the best configuration for your LPSPI would depend solely on the application's needs.

I hope this helps,
Edwin.

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