RT's System Clocks

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RT's System Clocks

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RT's System Clocks

This document describes the different source clocks and the main modules that manage which clock source is used to derive the system clocks that exists on the i.MX RT’s devices.

It’s important to know the different clock sources available on our devices, modifying the default clock configuration may have different purposes since increasing the processor performance, achieving specific baud rates for serial communications, power saving, or simply getting a known base reference for a clock timer.

The hardware used for this document is the following:

  • i.MX RT: EVK-MIMXRT1060

Keep in mind that the described hardware and management clock modules in this document are a general overview of the different platforms and the devices listed above are used as a reference example, some terms and hardware modules functionality may vary between devices of the same platform. For more detailed information about the device hardware modules, please refer to your specific device Reference Manual.

RT platforms

The Clock Controller Module(CCM) facilitates the clock generation in the RT platforms, many clocking variations are possible and the maximum clock frequency for the i.MX RT1060 device is @600MHz.The following image shows a block diagram of the CCM, the three marked sub-modules are important to understand all the clock path from the clock generation(oscillators or crystals) to the clock management for all the peripherals of the board.

 

javier_chavezq_19-1599155717168.png Figure 1. Clock Controller Module(CCM) Block Diagram

  1.        CCM Analog Submodule

This submodule contains all the oscillators and several PLL’s that provide a clock source to the principal CMM module.

For example, the i.MX RT1060 device supports 2 internal oscillators that combined with suitable external quartz crystal and external load capacitors provide an accurate clock source, another 2 internal oscillators are available for low power modes and as a backup when the system detects a loss of clock. These oscillators provide a fixed frequency for the several PLL’s inside this module.

Internal Clock Sources with external components

  •  Crystal Oscillator @24MHz

Many of the serial IO modules depend on the fixed frequency of 24 MHz. The reference clock that generates this crystal oscillator provides an accurate clock source for all the PLL inputs. 

  • Crystal Oscillator @32KHz

Generally, RTC oscillators are either implemented with 32 kHz or 32.768 kHz crystals. This Oscillator should always be active when the chip is powered on.

Internal Clock sources

  • RC Oscillator @24MHz

A lower-power RC oscillator module is available on-chip as a possible alternative to the 24 MHz crystal oscillator after a successful power-up sequence. The 24 MHz RC oscillator is a self-tuning circuit that will output the programmed frequency value by using the RTC clock as its reference.

While the power consumption of this RC oscillator is much lower than the 24MHz crystal oscillator, one limitation of this RC oscillator module is that its clock frequency is not as accurate.

  • Oscillator @32KHz

The internal oscillator is automatically multiplexed in the clocking system when the system detects a loss of clock. The internal oscillator will provide clocks to the same on-chip modules as the external 32kHz oscillator. Also is used to be useful for quicker startup times and tampering prevention.

Note. An external 32KHz clock source must be used since the internal oscillator is not precise enough for long term timekeeping.

PLLs

There are 7 PLLs in the i.MXRT1060 platform, some with specific functions, for example, create a reference clock for the ARM Core, USB peripherals, etc. Below these PLLs are listed.

  • PLL1 - ARM PLL (functional frequency @600 MHz)
  • PLL2 - System PLL (functional frequency @528 MHz)*
  • PLL3 - USB1 PLL (functional frequency @480 MHz)*
  • PLL4 - Audio PLL
  • PLL5 - Video PLL
  • PLL6 - ENET PLL
  • PLL7 - USB2 PLL (functional frequency @480 MHz)

* Two of these PLLs are each equipped with four Phase Fractional Dividers (PFDs) in order to generate additional frequencies for many clock roots.

 Each PLLs configuration and control functions like Bypass, Output Enable/Disable, and Power Down modes are accessible individually through its PFDs and global configuration and status registers found at the CCM internal memory registers.

  1.        Clock Control Module(CCM)

The Clock Control Module (CCM) generates and controls clocks to the various modules in the design and manages low power modes. This module uses the available clock sources(PLL reference clocks and PFDs) to generate the clock roots. There are two important sub-blocks inside the CCM listed below.

  • Clock Switcher

This sub-block provides the registers that control which PLLs and PFDs outputs are selected as the reference clock for the Clock Root Generator.

  •  Clock Root Generator

This sub-block provides the registers that control most of the secondary clock source programming, including both the primary clock source selection and the clock dividers. The clock roots are each individual clocks to the core, system buses, and all other SoC peripherals, among those, are serial clocks, baud clocks, and special function blocks. All of these clock references are delivered to the Low Power Clock Gating unit(LPCG).

  1.        Low Power Clock Gating unit(LPCG)

The LPCG block receives the root clocks from CCM and splits them to clock branches for each peripheral. The clock branches are individually gated clocks.

The following image shows a detailed block diagram of the CMM with the previously described submodules and how they link together.

javier_chavezq_20-1599155717393.pngFigure 2. Clock Management System

Example: Configure The ARM Core Clock (PLL1) to a different frequency.

The Clock tools available in MCUXpresso IDE, allows you to understand and configure the clock source for the peripherals in the platform. The following diagram shows the default PLL1 mode configured @600MHz, the yellow path shows all the internal modules involved in the clock configuration.

javier_chavezq_21-1599155717575.png Figure 3. Default PLL configuration after reset.

From the previous image notice that PLL1 is attached from the 24MHz oscillator, then the PLL1 is configured with a pre-scaler of 50 to achieve a frequency @1.2GHz, finally, a frequency divider by 2 let a final frequency @600MHz.

1.1 Modify the PLL1 frequency

For example, you can use the Clock tools to configure the PLL pre-scaler to 30, select the PLL1 block and then edit the pre-scaler value, therefore, the final clock frequency is @360MHz, these modifications are shown in the following figure.

javier_chavezq_22-1599155717898.png

 Figure 4. PLL1 @720MHz, final frequency @360MHz

   1.2 Export clock configuration to the project

After you complete the clock configuration, the Clock Tool will update the source code in clock_config.c and clock_config.h, including all the clock functional groups that we created with the tool. This will include the clock source for specific peripherals.
In the previous example, we configured the PLL1 (ARM PLL) to a functional frequency @360MHz; this is translated to the following structure in source code: “armPllConfig_BOARD_BootClockRUN” and it’s used by “CLOCK_InitArmPll();” inside the “BOARD_BootClockPLL150MRUN();” function.   

javier_chavezq_23-1599155717920.png

 Figure 5. PLL1 configuration struct

javier_chavezq_24-1599155717928.png

 Figure 6. PLL configuration function

Example: The next steps describe how to select a clock source for a specific peripheral.

1.1 Configure clock for specific peripheral

For example, using the GPT(General Purpose Timer) the available clock sources are the following:

  • Clock Source Off
  • Peripheral Clock
  • High-Frequency Reference Clock
  • Clock Source from an external pin
  • Low-Frequency Reference Clock
  • Crystal Oscillator

javier_chavezq_25-1599155718150.png

Figure 7. General Purpose Timer Clocks Diagram

Using the available SDK example project “evkmimxrt1060_gpt_timer” a configuration struct for the peripheral “gptConfig” is called from the main initialization function inside the gpt_timer.c source file, the default configuration function with the configuration struct as a parameter, is shown in the following figure.

javier_chavezq_26-1599155718155.pngFigure 8. Function that returns a GPT default configuration parameters

The function loads several parameters to the configuration struct(gptConfig), one of the fields is the Clock Source configuration, modifying this field will let us select an appropriate clock source for our application, the following figure shows the default configuration parameters inside the “GPT_GetDefaultConfig();” function.

javier_chavezq_27-1599155718507.png

 Figure 9. Configuration struct

In the default GPT configuration struct, the Peripheral Clock(kGPT_CLockSource_Periph) is selected, the SDK comes with several macros located at “fsl_gpt.h” header file, that helps to select an appropriate clock source. The next figure shows an enumerated type of data that contains the possible clock sources for the GPT.

javier_chavezq_28-1599155718534.png

 Figure 10. Available clock sources of the GPT.

For example, to select the Low-Frequency Reference Clock the source code looks like the following figure.

javier_chavezq_29-1599155718907.png

 Figure 11. Low-Frequency Reference Clock attached to GPT

Notice that all the peripherals come with a specific configuration struct and from that struct fields the default clocking parameters can be modified to fit with our timing requirements.

1.2 Modify the Peripheral Clock frequency from Clock Tools

One of the GPT clock sources is the “Peripheral Clock Source” this clock line can be modified from the Clock Tools, the following figure shows the default frequency configuration from Clock Tools view.javier_chavezq_31-1599155720592.png

Figure 12. GPT Clock Root inside CMM

In the previous figure, the GPT clock line is @75MHz, notice that this is sourced from the primary peripheral clock line that is @600MHz attached to the ARM core clocks.

For example, modify the PERCLK_PODF divider selecting it and changing the divider value to 4, the resulting frequency is @37.5Mhz, the following figure illustrates these changes.

javier_chavezq_32-1599155720607.png

 Figure 13. GPT & PIT clock line @37.5MHz

1.3 Export clock configuration to the project

After you complete the clock configuration, the Clock Tool will update the source code in clock_config.c and clock_config.h, including all the clock functional groups that we created with the tool. This will include the clock source for specific peripherals.

In the previous example, we configured the GPT clock root divider by a dividing factor of 4 to achieve a 37.5MHz frequency; this is translated to the following instruction in source code: “CLOCK_SetDiv(kCLOCK_PerclkDiv,3);” inside the “BOARD_BootClockRUN();” function.              

javier_chavezq_33-1599155720614.png

 Figure 14. Frequency divider function

References

i.MX RT1060 Processor Reference Manual

Also visit

LPC's System Clocks 

Kinetis System Clocks

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