RT1064 dcd/init files for HyperRAM project

[carstengroen]

I'm currently working on a RT1064 project (own hardware) that uses HyperRAM (S27KS0641). The HyperRAM device is working fine (at 0x60000000) and I can access the HyperRAM thru a testprogram (used the hyperram test project in the SDK as a basis). The code is running from the Flash inside the RT1064 (located at 0x70000000) and uses the OCRAM for data etc.

The HyperRAM is used in this project to save IO pins on the RT1064. Now, I wonder if there are some examples "out there", or someone who have done the xxxx_ini_dcd.c file, flexspi_nor_config.c  and debugger init files for HyperRAM ?

There are some very nice files with the SDK for the SDRAM, basically I'm after the same files but for HyperRAM (effectively replacing the SDRAM with HyperRAM). I know that it is not possible to have both data and code in the HyperRAM at the same time because of possible conflicts in the FlexSPI controller.

(would be nice also as there are HyperRAM on the 1064 EVK board, so some other might also be able to use it)

[p_shep]

Can actually do it on system initialisation, before the mem copies occur.

Goes a something a little like this:

static const clock_usb_pll_config_t usb1PllConfig_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src=0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};

/**
* System Initialisation Hook
* Called before all the data initialisations / copies
* called from SystemInit() in startup_MIMXRT1064.c
* Overrides the weak function in system_MIMXRT1064.c
*/
void SystemInitHook (void);
void SystemInitHook (void)
{
/* Set flexspi root clock to 332MHZ. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BootClockRUN);
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 27); /* Set PLL3 PFD0 clock 320MHZ. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* Divide the clock by 1 to get flexspi root clock 320MHZ */

__DSB();
__ISB();

/* Init hyperram */
PINS_HyperRam();
InitHyperRam();
}

void PINS_HyperRam(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0x10F1U);
}

void InitHyperRam(void)
{
    /* Follow guide, but note 
    * https://community.nxp.com/t5/i-MX-RT/RT1064-with-non-cacheable-area-in-HyperRAM-problem/m-p/12... 
    */
}

[jeremyzhou]

Hi Carsten Groen,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) I wonder if there are some examples "out there", or someone who have done the xxxx_ini_dcd.c file, flexspi_nor_config.c  and debugger init files for HyperRAM ?
-- I'm afraid it's impossible to initialize the HypeRAM successfully during the boot process like the SDRAM.
Have a great day,
TIC

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[p_shep]

Can actually do it on system initialisation, before the mem copies occur.

Goes a something a little like this:

static const clock_usb_pll_config_t usb1PllConfig_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src=0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};

/**
* System Initialisation Hook
* Called before all the data initialisations / copies
* called from SystemInit() in startup_MIMXRT1064.c
* Overrides the weak function in system_MIMXRT1064.c
*/
void SystemInitHook (void);
void SystemInitHook (void)
{
/* Set flexspi root clock to 332MHZ. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BootClockRUN);
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 27); /* Set PLL3 PFD0 clock 320MHZ. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* Divide the clock by 1 to get flexspi root clock 320MHZ */

__DSB();
__ISB();

/* Init hyperram */
PINS_HyperRam();
InitHyperRam();
}

void PINS_HyperRam(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0x10F1U);
}

void InitHyperRam(void)
{
    /* Follow guide, but note 
    * https://community.nxp.com/t5/i-MX-RT/RT1064-with-non-cacheable-area-in-HyperRAM-problem/m-p/12... 
    */
}

[p_shep]

Can actually do it on system initialisation, before the mem copies occur.

Goes a something a little like this:

static const clock_usb_pll_config_t usb1PllConfig_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src=0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};

/**
* System Initialisation Hook
* Called before all the data initialisations / copies
* called from SystemInit() in startup_MIMXRT1064.c
* Overrides the weak function in system_MIMXRT1064.c
*/
void SystemInitHook (void);
void SystemInitHook (void)
{
/* Set flexspi root clock to 332MHZ. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BootClockRUN);
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 27); /* Set PLL3 PFD0 clock 320MHZ. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* Divide the clock by 1 to get flexspi root clock 320MHZ */

__DSB();
__ISB();

/* Init hyperram */
PINS_HyperRam();
InitHyperRam();
}

void PINS_HyperRam(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0x10F1U);
}

void InitHyperRam(void)
{
    /* Follow guide, but note 
    * https://community.nxp.com/t5/i-MX-RT/RT1064-with-non-cacheable-area-in-HyperRAM-problem/m-p/12... 
    */
}

[BlackTurbo]

Is that means that the HyperRAM can't be initialized using DCD?

[carstengroen]

Thanks jeremyzhou‌,

I have made a temporary fix (which then will be permanent it seems :smileywink:), my bootloader, which can survive with only the internal RAM of the RT1064, initializes the HyperRAM before it executes the primary firmware (which uses the HyperRAM). As a sidenote, I'm running a Dhrystone test, if I run the test in internal SRAM (DTCM) I get around 30 mS for 100.000 iterations, if I place data in HyperRAM I get around 65 mS for the same number of iterations (just if anyone wonders about performance). This is without any tuning of parameters for HyperRAM (if there is anything to tune, still using the values from the FlexSPI HyperRAM sample from SDK).