RT1050 QSPI flash configuration for alternate flash with GNU toolchain

[joshuasakwa]

For our design we plan to use flash W25Q32JV and it looks like we will need to change the SPI Flash register format the same way as AN12183. However, I couldn't find any definition for ISSI_CMD_WRSR in the EVK code-base. Additionally I was not able to find the code-fragment containing the WriteStatusReg8 etc. I'm using EVK version 2.3.1 with GNU toolchain. Do I need to use IAR to make these changes?

Changes suggested by AN12183 summarized below:

A couple of related questions:

• Am I correct to assume that: "FLEXSPI_LUT_INST" has been replaced by "FLEXSPI_LUT_SEQ", and the format changed?
• Do you have any documentation on this format?

Thanks in Advance,

Joshua

[noahwang]

Hi Joshua,

You are correct that FLEXSPI_LUT_SEQ is the correct macro to use.

You need to make the following modifications to use quad IO read in your LUT (assuming your part is the IQ variant with Quad Enable set by default):

.lookupTable =
{
   // Quad IO Read
   FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
   FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x08)
},

[ebollerman]

What about the case for the IS25LP064A where the Quad enable bit is off by default? I am having issues finding the correct LUT sequence for this case and part. Do you happen to know what that would be?

[noahwang]

Just typing out some code off the top of my head here so you may need to correct some errors, but this should give you an example of what you can do.

Add these to the FlexSPI NOR config:

.deviceModeCfgEnable = true,

.deviceModeSeq = { 1, 2 }, // This stands for execute 1 sequence starting from sequence 2 (so it will only run sequence 2)

.deviceModeArg = 0x40, // corresponds to the quad enable bit in the status register

Change your LUT to this, I've provided just the sequences for quad read and quad enable so you'll need to re-add any other ones that you were using

// 0 Quad read
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x08),
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),

// 1 (should be read status)
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),

// 2 Custom sequence: set status register
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x01),

The custom sequence and the argument are all from the datasheet of the IS25LP064A.

[alain_olivier]

Very useful Noah! Thanks.

I'm just wondering what is the difference between deviceMode and configCmd related entries. These seem to be structured in the same way but it is not clear what they do.

Wouldn't it be more correct to use configCmd to set registers?

Thanks,

Alain.

[joshuasakwa]

Thanks Noah,

That's great information... but in my case I want to work with a device that has a register format that differs form the QSPI device on the EVK. The register format on my device is more similar to GD25Q64C (sighted in the application note in "5.4.2. How to program the image to GD25Q64C") Is that something that could be supported?

Thanks Again!

Joshua

[noahwang]

Hi Joshua,

The macros in the application note are different from those provided by the EVK, I am more familiar with the EVK so I can't explain what defines such as ISSI_CMD_WRSR are. However I see what they are trying to do is execute the write status register command. When dealing with NOR flash, writing to the status register is most commonly used for enabling quad IO, setting the number of dummy cycles to run at different frequencies, or changing burst length. You shouldn't need to do either of these since the datasheet of that Winbond parts indicates that Quad Enable is set by default, and there doesn't seem to be any option to set dummy cycles. Therefore, I think that you don't even need to define a write status register sequence in the LUT, purely the read sequence should be enough.

For the read sequence, I have set it based on the datasheet you have linked (section 8.2.11 Fast Read Quad I/O)

The first instruction in the sequence is sending the 0xEB command over single wire

The second instruction is writing the 24 bit address over four wires

The third instruction represents the 2 clocks for mode, and 4 clocks for dummy, I didn't send any mode so I've made all 6 clocks dummy

The fourth instruction represents receiving 8 bytes over four wires (8 is the default burst length according to the datasheet)

Let me know if this doesn't work for you, I can provide a full flexspi_nor_config_t struct for you when I have time.

For a list of all sequences that can be used for NOR flash, see table 8-15 in the reference manual. You can implement the other sequences based on the Winbond datasheet if you want to use them for IP/AHB instructions.

[joshuasakwa]

Thanks for supplying the extra context! From what you've explained so far, it sounds like this config should at least enable the part to boot. In terms of getting the code onto an unprogrammed device, will I need to pre-program the flash with an image that has these settings, or does the serial flash loader associated with the ROM image, have sufficient flexibility to perform this procedure?

Thanks again for all of your help!

Joshua

[noahwang]

Happy to help Joshua, I was pretty much dealing with the same questions about the flash and SDRAM 2 weeks ago. For loading firmware onto the device with your own flash configuration, you can either use either LPC-Link, JTAG (I've been using this), or the serial downloader. I think if you use the Kinesis flashloader and the mfgtool, elftosb will generate it's own flash config based on what you've defined in the .bd file (In all the examples I've seen, NXP just tells you what to put in the file but doesn't explain how to customise it). I've never tried to load my own flash config through the flashloader, though the config generated by elftosb works fine for the ISSI flash chip on the EVB.