Question about evkmimxrt1064_flexspi_nor_config.c

[mjbcswitzerland]

Hi All

This is the QSPI flash configuration as used for booting the iMXRT1064 EVK:

const flexspi_nor_config_t qspiflash_config = {
    .memConfig =
        {
            .tag              = FLEXSPI_CFG_BLK_TAG,
            .version          = FLEXSPI_CFG_BLK_VERSION,
            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
            .csHoldTime       = 3u,
            .csSetupTime      = 3u,
            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
            .sflashPadType = kSerialFlash_4Pads,
            .serialClkFreq = kFlexSpiSerialClk_100MHz,
            .sflashA1Size  = 8u * 1024u * 1024u,
            .lookupTable =
                {
                    // Read LUTs
                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
                },
        },
    .pageSize           = 256u,
    .sectorSize         = 4u * 1024u,
    .blockSize          = 256u * 1024u,
    .isUniformBlockSize = false,
};
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As far as I have understood the chip boots from its internal 4MB QSPI flash chip (on FlexSPI2 and at 0x70000000) but there are two entries in the table that I don't understand:

1.

.sflashA1Size  = 8u * 1024u * 1024u,

Should this not be 4M and not 8M?

2.

.blockSize          = 256u * 1024u,

The internal QSPI flash (W25Q32JV) has 64k block size and not 256k block size?

Are these entries incorrect but on non-importance or is there another explanation?

Regards

Mark

[victorjimenez]

Hi Mark, 

Thanks for reporting this! I already reported it with the SDK team and this will be fixed in future releases. As long as you don't use a flash size greater than 4MB you won't get any issues with this configuration.

Regards,

Victor 

[mjbcswitzerland]

Victor

Is there any details about the importance of the 256k block size?

Regards

Mark

[victorjimenez]

Hi Mark, 

The block size is consistent with flash size, you can look at them as one parameter and it only impacts the register FLASHA1CR0. This will only cause a problem when the desired access flash address is more than the actual flash size (4MB). 

Regards,

Victor