Problem configuring FlexRAM with DCD on i.MX RT1064

[green-panda]

Hi,

I would like to store a Zephyr application in the integrated flash (FlexSPI2), but execute from ITCM memory. The ROM RAM-loader can copy the executable to ITCM. But the FlexRAM has to be configured before so that the ITCM has enough capacity. I would like to do this with device configuration data (DCD), because the fuse configuration does not offer the specific configuration that I would like to use.

To get started, I added a register write to IOMUXC_GPR_GPR17 to the DCD. I did not yet write to IOMUXC_GPR_GPR16 to activate the FlexRAM config in IOMUXC_GPR_GPR17. By default, the FlexRAM config from the fuses is used. But even just by writing to IOMUXC_GPR_GPR17 the ROM seems to refuse to execute other parts of or the whole DCD. I checked that for example IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, which is part of the default DCD of the MIMXRT1064-EVK board, will get written without my DCD modification, but will not be written with my modification. I used the J-Link GDB server and GDB to read out the registers after booting.

With modification:
C:\Users\user\zephyr-sdk-0.16.3\arm-zephyr-eabi\bin>arm-zephyr-eabi-gdb.exe
...
(gdb) file C:/Users/user/zephyrproject/zephyr/build/zephyr/zephyr.elf
Reading symbols from C:/Users/user/zephyrproject/zephyr/build/zephyr/zephyr.elf...
(gdb) target remote localhost:2331
Remote debugging using localhost:2331
arch_cpu_idle () at C:/Users/user/zephyrproject/zephyr/arch/arm/core/cortex_m\cpu_idle.S:139
139 cpsie i
(gdb) monitor memU32 0x400AC044
Reading from address 0x400AC044 (Data = 0x00000000) (IOMUXC_GPR_GPR17, should be 0xFFFFFA55)
(gdb) monitor memU32 0x401F8014
Reading from address 0x401F8014 (Data = 0x00000005) (IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, should be 0x00000000)

If I do a write to an OCRAM2 location (0x20240000) instead of IOMUXC_GPR_GPR17, I can read out the expected values for both the OCRAM2 location as well as IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 after boot. So I assume that at least my workflow for creating the DCD is working.

The reference manual of the RT1064 states in section 9.7.2.1 "Write data command":
"If any of the target addresses do not lie within the allowed region, none of the values are written." But table 9-25 "Valid DCD address ranges" states that 0x400AC000 - 0x400AFFFF should be allowed, so IOMUXC_GPR_GPR17 should be allowed.

What's the problem here?

AN12077 states "It is not recommended to reconfigure the FlexRAM memory using DCD (Device Configuration Data) due to a potential conflict with the ROM code memory allocation." According to the reference manual of the RT1064 section 9.5.1, the ROM code uses 0x20200000 - 0x20207FFF for volatile memory. This is OCRAM2 and not part of the FlexRAM. So there should be no conflict on the RT1064, right?

[Omar_Anguiano]

Hello
I hope you are well.

I suggest you write to these registers on the Reset Handler since that part of the code manages the FlexRAM configuration. It is possible that Reset handler is overwriting your DCD config.
This document has some reason why you should configure the flexram through the fuses, it may cause some software issues, additionally there are configurations that are not allowed, such as leaving OCRAM to 0Kb.

Reallocating the FlexRAM - NXP Community

Best regards,
Omar