On an RT106x, how do you use SEMC_MCR.DQSMD = 0 (to free up EMC_39 for a spare GPIO)?

[np]

Hi everyone,

An RT106x board with SDRAM I've been asked to look at has been designed to use EMC_39 as a spare GPIO. Reading the Reference Manual, it seems the way to configure the registers for this would be to set DQSMD = 0 (in the SEMC_MCR register) and then set up the ALT5 pinmux for EMC_39.

However, even though the SDRAM currently works fine with DQSMD = 1, the moment I set DQSMD to 0 the SDRAM stops working (and this is in EMC_39's ALT0 pinmux mode, never mind the ALT5 mode).

My best guess is that the SEMC timings for the SDRAM would need to be edited in order to get DQSMD = 0 working, but I think I'm missing some key information to achieve this.

What would I need to do to get DQSMD = 0 this working? Is DQSMD = 0 (disabled) much slower than DQSMD = 1 (enabled)?

All hints and suggestions gratefully received!

Thanks, Nick

PS: the two closest posts I found were this RT1050 one from 2019 by David Rodgers ( @dmarks_ls

https://community.nxp.com/t5/i-MX-RT/RT1050-Can-SDRAM-DQS-be-looped-back-internally/m-p/907390

...and this RT1020 post from 2020 by Ronnie Shipman ( @rshipman

https://community.nxp.com/t5/i-MX-RT/RT1020-clocking-SDRAM-at-166Mhz-Zero-timing-margin/m-p/1039370

[np]

Note #1: I know that the DQSMD setting is editable via the SEMC configuration structure in the SEMC peripheral, i.e. Dummy read strobe mode = "Dummy read strobe loopbacked internally". But I don't know how to recalculate the SDRAM configuration settings to make it actually work.

Note #2: it seems @mjbcswitzerland may have attempted something along these lines, as per:

https://community.nxp.com/t5/i-MX-RT/Why-does-the-SDK-s-evkmimxrt1060-sdram-ini-dcd-c-configure-all/...

[mjbcswitzerland · Accepted solution]

Hi

In order to move from DQSMD 1 to DQSMD 0 you must (first) reduce the SEMC_CLK_ROOT speed to about 60MHz.

From the data sheet it is seen that 133/166MHz speed is not supported when using the alternative configuration:

See pages 20..21 of https://www.utasker.com/docs/iMX/i.MX_RT_1021_uTasker.pdf for SEMC clock settings and check how it is set as default (eg. via DCD) then increase the root divide value (SEMC_PODF) in CCM_CBCDR accordingly.

This can either be done generally in the DCD or else the DCD can be set for full speed and then the change be made on-the-fly when the GPIO is needed - note however that the pin should usually be left floating for the highest speed of operation ad not connected to external circuitry.

Regards

Mark
[uTasker project developer for Kinetis and i.MX RT]
Contact me by personal message or on the uTasker web site to discuss professional training, solutions to problems or rapid product development requirements

For professionals searching for faster, problem-free Kinetis and i.MX RT 10xx developments the uTasker project holds the key: https://www.utasker.com/iMX/RT1060.html

[np]

Thanks, Mark, that's really helpful, you're a star!