Hello,
I’m working with an RT1176 EVK, my goal is to enable the Master LPSPI QSPI interface. The QSPI interface is connected to an FPGA. I was able to get the QSPI transmit side to successfully send packets of variable lengths to the FPGA. The FPGA properly decoded the QSPI data. However, I’m having issues on the read side.
I’m using the APP note “Using LPSPI on the KL28Z”as a reference (Document Number: AN5320) on how to configure the LPSPI QSPI.
In effort to simplify things the ARM is not transmitting, only receiving. Also the FPGA is setting the D0-D3 signals high, so all of the incoming data should be 0xF.
Before entering the main loop I have the following configuration.
//set to 4 bit transfer
EXAMPLE_LPSPI_MASTER_BASEADDR->TCR = (EXAMPLE_LPSPI_MASTER_BASEADDR->TCR & ~LPSPI_TCR_WIDTH_MASK) | LPSPI_TCR_WIDTH(2);
//PCS[3:2] are configured for half-duplex 4-bit transfers
EXAMPLE_LPSPI_MASTER_BASEADDR->CFGR1 = (EXAMPLE_LPSPI_MASTER_BASEADDR->CFGR1 & ~LPSPI_CFGR1_PCSCFG_MASK) | LPSPI_CFGR1_PCSCFG(1);
//clear to enable receiving
EXAMPLE_LPSPI_MASTER_BASEADDR->TCR = (EXAMPLE_LPSPI_MASTER_BASEADDR->TCR & ~LPSPI_TCR_RXMSK_MASK);
//set to begin reading transfer
EXAMPLE_LPSPI_MASTER_BASEADDR->TCR = (EXAMPLE_LPSPI_MASTER_BASEADDR->TCR & ~LPSPI_TCR_TXMSK_MASK) | LPSPI_TCR_TXMSK(1);
In the while(1) loop, I have the following configuration and I read the RDR register, which is 32 bits.
//clear to enable receiving
EXAMPLE_LPSPI_MASTER_BASEADDR->TCR = (EXAMPLE_LPSPI_MASTER_BASEADDR->TCR & ~LPSPI_TCR_RXMSK_MASK);
In the APP note it lists the configuration needed to enable the QSPI interface. Part of the configuration from the 4-bit sending operation section 3.3.1 is also needed for the Read operation (highlighted in yellow).
I’m probing the QSPI signals with an Oscope. I see 8 clock cycles per transaction, and 0xFF printed on the terminal, when it should be 0xFFFFFFFF. It’s as if the receive isn’t configured as QSPI, but instead as SPI.
Questions:
Does anyone have any examples of how to configure the LPSPI QSPI to read multiple bytes?
Am I missing a configuration register that I need to set/clear to get the reads to work properly?
Thanks,
Ricardo
- What EVK version are you using A or B?
- I'm using an Embedded Artist EVK
- https://www.embeddedartists.com/products/imx-rt1176-developers-kit/
- What SDK version are you using?
- I started off with the LPSPI -> polling_b2b_transfter -> master -> cm7 example project
- The SDK version that I am using was provided by embedded artist. It seems to be very similar to the NXP's SDK, but obviously has modifications to the code so it can run on the embedded artist RT1176 EVK
- http://imx.embeddedartists.com/#imxrt1176
- IDE version
- Keil uVision 5 (V5.27.1.0)
- How are you connecting the QSPI interface to your FPGA?
- I'm connecting CLK, CS, D0, D1, D2, D3 from the J15 connector on the RT1176 EVK to a PMOD header on the FPGA EVK
I was able to successfully read 32 bits from the FPGA. The problem was that the default LPSPI project was configuring SDO in the wrong way. SDO was being told to retain its value. This was causing weird issue where sometimes I would properly decode the 32 bit word and other times I would not. See highlighted.
I had to make the following change.
I'm now working on transferring larger packets sizes.
Thanks for the links. I will take a look at them.
Thanks,
Ricardo
