Hi All,
I want to interface SAI3 in imxrt106s with an audio codec .Audio codec will be the slave and IMXRT106s will be the master. MCLK needed for the audio codec will be given by SAI3. What is the default MCLK value of SAI3 in sln-local2-iot sdk and how can we control the mclk frequency?I have configured GPIO_EMC_37 as MCLK(direction output) .While probing clock frequency,it is showing as 12MHz. How can we confirm whether it is correct or not?
Please guide me to configure the mclk
Thanks in advance!
Hello,
Did you review the application notes, AN13208, AN13363, AN_RT1060_v1.5 [Audio performance requirements for Audio Front End of i.MX RT106A/L/S and i.MX RT105S] and AN13212 may be could help you, I will download the SDK for review if there is any more information.
Best regards,
Pavel
Hello,
Could you tell me if you are using the evaluation board o only have the MCU? I have already the SDK installed, Could you tell me the example you are based on?
Best regards,
Pavel
Hello,
I'm following your case, sorry for the late response I was trying to get an SLN-LOCAL2 to test it, but I review the code and I compared it to other examples in the RT1064.
I'm unavailable to find the code like this.
wm8960_config_t wm8960Config = {
.i2cConfig = {.codecI2CInstance = BOARD_CODEC_I2C_INSTANCE, .codecI2CSourceClock = BOARD_CODEC_I2C_CLOCK_FREQ},
.route = kWM8960_RoutePlaybackandRecord,
.leftInputSource = kWM8960_InputDifferentialMicInput3,
.rightInputSource = kWM8960_InputDifferentialMicInput2,
.playSource = kWM8960_PlaySourceDAC,
.slaveAddress = WM8960_I2C_ADDR,
.bus = kWM8960_BusI2S,
.format = {.mclk_HZ = 6144000U, .sampleRate = kWM8960_AudioSampleRate16KHz, .bitWidth = kWM8960_AudioBitWidth16bit},
.master_slave = false,
};
codec_config_t boardCodecConfig = {.codecDevType = kCODEC_WM8960, .codecDevConfig = &wm8960Config};
So let me get more information, I will ask to another team.
Best regards,
Pavel
Hello,
--> What is the default MCLK value of SAI3 in sln-local2-iot SDK
Based on sln-local2-iot SDK, SAI3 CLK is provided by Audio/Video PLL CLK(786.48MHz)
And MCLK divider is 64, so the SAI3 MCLK is 768.48/64 = 12.28875MHz. Except for the MCLK, Need to check BCLK and sync clock.
--> How to configure MCLK
Example:
/*Clock setting for SAI3*/
CLOCK_SetMux(kCLOCK_Sai3Mux, BOARD_AMP_SAI_CLOCK_SOURCE_SELECT);
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, BOARD_AMP_SAI_CLOCK_SOURCE_PRE_DIVIDER);
CLOCK_SetDiv(kCLOCK_Sai3Div, BOARD_AMP_SAI_CLOCK_SOURCE_DIVIDER);
BOARD_SAI_Enable_Mclk_Output(SAI3, true);
Best regards,
Pavel
Hello,
I suggest modifying the macro [BOARD_AMP_SAI_CLOCK_SOURCE_DIVIDER] to change the result in Hz.
Best regards,
Pavel
Hello,
This is how the macro affects the MCLK.
MCLK = PLL audio clock / (BOARD_AMP_SAI_CLOCK_SOURCE_PRE_DIVIDER + 1) / (BOARD_AMP_SAI_CLOCK_SOURCE_DIVIDER + 1)
Best regards,
Pavel