High speed counter measurements on a MIMXRT1176 board

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High speed counter measurements on a MIMXRT1176 board

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Oliver_R
Contributor I

Hi,

We have the following, quite demanding task:

We have to count some very short pulses (min. ~7 ns) on two channels for some kind of correlation function. I know I can clock the counter module on this chip up to 240 MHz, so this should be possible.

For the correlation function it is necessary to:

  1. Read both counters (lower 8 bit are enough) in exact time slices of around 100 ns
  2. Copy the counters into a circular buffer
  3. Compress the data and write it to some large data buffer

So it is clear, that step 1 and 2 must be done without any software interaction (e.g. interrupts). In principle it should be possible to set up the PIT module of the chip to 10 MHz in order to trigger the eDMA. The the eDMA can copy the data with high priority from the counter registers to a location in memory.

Using the scatter/gather mode of the eDMA, a circular ring buffer should also be possible (the alternative eDMA modulo function is restricted to 32 transfers).

What I don't know and what I don't find in the data sheet: Although there are no interrupts involved in step 1 and 2, I don't know if the eDMA setup times (triggered by the PIT module) are low enough. I have no idea of jitter times or the transfer times.

Maybe the necessary timing here is too demanding for the chip and I have to use some additional hardware?

A different idea would be to readout a dedicated counter IC by the FlexIO periphal in some kind of SPI mode but with 4 or 8 bits reading simultaneously. Setting the FlexIO SPI frequency to 10 MHz should be no problem at all, but the pin synchronization of the counter IC is a problem here (there are buffered counter ICs on the market, but they were too slow).

So, any suggestions if my first idea has a chance to work? Any other ideas for resolving this task are welcome, too.

Thanks any bye,
Oliver

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Kan_Li
NXP TechSupport
NXP TechSupport

Hi @Oliver_R ,

 

Yes, the input capture would make much more sense here, and it can trigger a DMA operation for sure, please kindly refer to the DMA MUX Mapping table for details.

Kan_Li_0-1698997011984.png

 

Have a great day,
Kan


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Kan_Li
NXP TechSupport
NXP TechSupport

Hi @Oliver_R ,

 

May I know the source and destination of the DMA operation? From some register to the SRAM? Please kindly clarify.

 

Have a great day,
Kan


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Oliver_R
Contributor I

Hi Kan,

source is the GPT_CNT register or the quad timer counters (TMR) , destination is a (circular) buffer in the SRAM.

 

Another option would be the input capture function. It should be fast enough, but I couldn't find a DMA trigger for a capture event. And the optional capture IRQ is much too slow (I read about 40-60 ns for entering the IRQ).

 

Thanks and bye, Oliver

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Kan_Li
NXP TechSupport
NXP TechSupport

Hi @Oliver_R ,

 

Yes, the input capture would make much more sense here, and it can trigger a DMA operation for sure, please kindly refer to the DMA MUX Mapping table for details.

Kan_Li_0-1698997011984.png

 

Have a great day,
Kan


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- We are following threads for 7 weeks after the last post, later replies are ignored
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Oliver_R
Contributor I
This sounds promising. I'll check it out!

Thanks and bye,
Oliver
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