Hard fault noticed when only internal DATA ram is selected for global variables

[FW_racer]

Hi

We are working on a custom board based on RT1062 and we have a peculiar problem, hoping if there could be some help through this channel. Our SW stack is ported from K66 to RT1062 and we are trying to just use the external flash(FlexSPI) and internal RAM on RT1062. App image is executed from FlexSPI flash in XIP mode.

Issue : Global variables if forced to an internal RAM section (Flexram_Data) is causing a Hardfault and upon probing it is a bus error. But we don't notice this hardfault if we map the global variables to internal instruction memory (which doesn't seem right as data needs to stay with in the data section). Based on hardfault analysis we could infer it is a bus fault but failing to understand why it doesn't show up when set to instructino memory. All i can think of is alignment but again the alignment is 4 byte for both sections (inferred through the linker). Does the access would still be 8byte for instruction memory as the bus width is 8 byte, does it help forcing the alignment for internal data section as well to 8 byte ??

[FW_racer]

Hi Kerry, thanks for your response. I am using the default config(from efuses) and not using register settings to reconfigure the FlexRAM. What i have noticed though is that the linker file even though it is indicating that the memory section of SRAM_ITC is of 4 bytes alignment but when i analyze through the objdump it is indicating it is 8 byte aligned. Could you please clarify this as I am doubting if it is contributing to the behavior I am seeing as when the global data resides in memory area which is accessed as 8 byte aligned it might not be causing an issue Vs when it is accessed as though it is 4 byte aligned. Having said that the cortexM7 should not flag a hard fault but the registers indicate that the hardfault is forced as in through escalation of some exception/fault.

[kerryzhou]

HI @FW_racer ,

  Thanks so much for your information.

  Could you please share some picture about your description:

 the linker file even though it is indicating that the memory section of SRAM_ITC is of 4 bytes alignment but when i analyze through the objdump it is indicating it is 8 byte aligned.

 I mean:

1.linker file with SRAM_ITC is 4bytes alignment,

2. objdump is 8 bytes aligned

BTW, can you reproduce the hardfault issues with 4 bytes alginment with the NXP SDK and the EVK board? Just also let me reproduce the issues, you also can delete your important code, just let the simple project which can reproduce the issues, then share it to me, I will help you to test it on myside.

Best Regards,

Kerry

[kerryzhou]

Hi @FW_racer ,

  Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.

 You mentioned:l RAM section (Flexram_Data) is causing a Hardfault 

  What's the detail flexRAM you are using, in fact, it is the ITCM, DTCM, Ocram, you need to make sure the default ITCM, DTCM, OCRAM is not oversize with your app.

  By the way, you also can try to disable the cache if you use the OCRAM, I think 4 byte align is OK to use.

If you still have issues about it, please kindly let me know.

Best Regards,

Kerry