ENET lwip_bm_cm7 flashing issues

[ManikantaRobbi]

Hi,

we had designed a custom board RT-1176 with QSPI IS25WP128-JKLE-TR connected. All peripherals are tested with examples provided in MCUXpresso IDE. But we had failed to Test ENET port. we tried with lwip_ping_bm_cm7.  Required IP address is changed. This example is working on EVK kit. But when tried to flash in Our custom board it giving HARDFAULT issue. Here I had attached the schematic of ENET and RJ-45 port, RMI 100M.

[Kan_Li]

Hi @ManikantaRobbi ,

No critical issue found in the schematics, but looks there are two clock signals on XI of the PHY chip, please make sure if only one of them is available on your board, otherwise there might be issue.

Have a great day,
Kan

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[ManikantaRobbi]

Thanks for reply,

We probed TX&RX data pins, which are generating signals similar to EVK. But here attached image below we are getting status 4003 (kStatus_ENET_RxFrameEmpty) instead of 0. when we debug further.

,

Here it should go to else part, but if becomes true curBuffDescrip->control due to this structure.

We are receiving the differential signals at RX0 & RX1. still the buffer shows empty. Kindly help me to resolve this issue ASAP.

Thanking you,

Manikanta Robbi.

[ManikantaRobbi]

Difference while flashing EVK vs Custom Board.

[Kan_Li]

Hi @ManikantaRobbi ,

Maybe you can try to run the demo in SDRAM as below:

Please kindly let me know if the problem is still there.

Have a great day,
Kan

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[ManikantaRobbi]

Hi @Kan_Li ,

Thanks for support.

Issue revolves around the CSR/DV pin behavior. In the ideal scenario and observed in the EVK kit, the CSR/DV pin shifts from low to high before data reception, enabling data processing.

However, in the new board design, this pin remains persistently low, inhibiting the MAC/controller from triggering the NAVIC engine and processing incoming data. This discrepancy obstructs data recognition and hampers processing.

Rectifying the constant low state of the CSR/DV pin in the new design board is crucial. Aligning the CSR/DV pin behavior with the expected pattern is essential for enabling proper data reception and processing within the MAC/controller interface.

Please go through images attached below, which exhibits difference EVK vs Custom Board.

And also I want know is  CSR/DV is same as  pin RX_EN in RMII mode.

[ManikantaRobbi]

Hi @Kan_Li ,

Thanks for reply.
CRS_DV pin is connected to GPIO_DISP_B2_08,  same as EVK.

Kindly go through our Custom Board schematic.

As per your information we need to check RX[1:0] signals whether it is changing to preamble. Or any changes need to be done in programming part.

Above image is reception of data with respect to CRS_DV. I think PHY chip is trying to pull-up to 3V3. we remove connection between MAC and Check PHY end we are getting same appropriate signal.

And I had one doubt  in which mode the respective pin acts as CRS_DV pin is also RX_EN.

Thanks & Regards,

Manikanta Robbi.

[Kan_Li]

Hi @ManikantaRobbi ,

CRS_DV signal is an input to the RT device, and this signal is connected with the pin of GPIO_DISP_B2_08 on the EVK board, please kindly check it on your board . Please also refer to the following for more details.

Have a great day,
Kan

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[ManikantaRobbi]

Thanks for support,

we are happy to say that code is flashing well using JTAG. Steps performed exported working project xml memory file and imported the same.

Now HARDFAULT issue is resolved.

Now can we are able to ping i.e. send default gateway by not receiving echo from the other end.

1.Kindly guide me with this issue, like which pins are need to be tested.

a)TX_DATA0

b)TX_DATA1

c)RX_DATA0

d)RX_DATA1

e)REF_CLK.

and anything we missed and more info about status/activity led on RJ-45 connector.

Note: evkmimxrt1170_lwip_ping_bm_cm7 same code imported from IDE, working fine on EVK kit in 100M configuration but failed to receive echo on Custom-board.

Thanking you,

Manikanta Robbi.

[ManikantaRobbi]

Thanks we had removed 0ohm resistor now we are providing only one clock source.

[Kan_Li]

Hi @ManikantaRobbi ,

Which clock is used as the reference? 

Best Regards,

Kan

[ManikantaRobbi]

 Hi @Kan_Li ,

This is the Memory configuration, which is default when we import any SDK examples. And Especially in ENET lwip examples this config is working fine in EVK.

But when we flashed in our Custom board it runs continuously, and throwing Hard Fault memory issue. 

This is got solved by import this XML file.

I had seen RAM order is different in both, but can you say the reason why above configuration is working in our board, rather than default given by IDE.

[ManikantaRobbi]

We are receiving 50MHz clock and data on TX0,TX1,RX0 & RX1. but unable to get ping receive on Serial Console.