iMX-RT1175 SPI NOR Boot

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iMX-RT1175 SPI NOR Boot

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danielberhe
Contributor IV

Hi All,

I'm having issues booting my custom IMXRT1175AVM8A based board. I'm using Micron MT25QL256ABA1EW7 flash chip and it is wired as shown below:

danielberhe_0-1699530640754.png

I used a modified version of the SDK flexspi sample project (see attachement) to test the flash and the test succeeds when it is linked to RAM. I modified the sample project to use one pad instead of 4 as the function flexspi_nor_enable_quad_mode was writing to the status register to enable quad mode but enabling quad on my flash device is done by writing to a different register. I'm currently modifying the project further to enable quad properly.

I've modified the nor config struct:

const flexspi_nor_config_t qspiflash_config = {
    .memConfig =
        {
            .tag              = FLEXSPI_CFG_BLK_TAG,
            .version          = FLEXSPI_CFG_BLK_VERSION,
            .readSampleClksrc=kFlexSPIReadSampleClk_LoopbackInternally,
            .csHoldTime       = 3u,
            .csSetupTime      = 3u,
            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
            .controllerMiscOption = 0x10,
            .deviceType           = kFlexSpiDeviceType_SerialNOR,
            .sflashPadType        = kFlexSpiSerialClk_60MHz,
            .serialClkFreq        = kFlexSpiSerialClk_60MHz,
            .sflashA1Size         = 32u * 1024u * 1024u,
            .lookupTable =
                {
                    // Read LUTs
                    [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_1PAD, 0x18),
                    [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 0x06, READ_SDR, FLEXSPI_1PAD, 0x04),

                    // Read Status LUTs
                    [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),

                    // Write Enable LUTs
                    [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),

                    // Erase Sector LUTs
                    [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),

                    // Erase Block LUTs
                    [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),

                    // Pape Program LUTs
                    [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),
                    [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),

                    // Erase Chip LUTs
                    [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),
                },
        },
    .pageSize           = 256u,
    .sectorSize         = 4u * 1024u,
    .ipcmdSerialClkFreq = 0x1,
    .blockSize          = 64u * 1024u,
    .isUniformBlockSize = false,
};

 

Due to a hardware design error I currently don't have access to UART1 or USB1 so I can't use blhost or something similar to serial download or burn fuses that way. So I modified the OCOTP SDK sample project to burn BT_FUSE_SEL. I set EXAMPLE_OCOTP_FUSE_MAP_ADDRESS to 0x16 and EXAMPLE_OCOTP_FUSE_WRITE_VALUE to 0x10.

I checked what's in flash using J-Link and it looks correct but I will do byte by byte comparison to be on the safe side.

Attempting to debug any of my projects fails and I see this

danielberhe_1-1699533422891.png

I've checked that pins BOOT_MODE[1:0] are set to 00.

Can anyone see where I'm going wrong?

Thanks,

Daniel

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5 Replies

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nxf77486
NXP TechSupport
NXP TechSupport

Hello,

Can you please help me by giving a look into the following application note that can be useful.

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974 Views
danielberhe
Contributor IV

Hello,

I have had a look at the document but didn't find any information to help solve my issue. I cannot use MFG tool with my custom board because as there was a hardware design error and the board cannot be found either through USB or UART when in serial download mode.

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nxf77486
NXP TechSupport
NXP TechSupport

Hello

Also please find the hardware development guide that can be helpful for you custom board design.

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948 Views
danielberhe
Contributor IV

Thank you for the link. We are already aware of the hardware issue on our custom board and the design issue will be fixed on the next revision.

Am I to understand that the only way to solve my issue is by using MFGTool and I can't do it through MCUXpresso?

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978 Views
danielberhe
Contributor IV

Hello,

Apologies for the late reply. I didn't receive a notification email for some reason. I will have a read and report back.

Thanks,

Daniel

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