3-wire SPI on RT1170

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DCheung
Contributor II

The post https://community.nxp.com/t5/i-MX-RT/3-line-SPI-configuration-for-send-and-receive-data-at-the-same/... has had an answer involving modification to the nxp driver. It's been 2 years and I wonder if there are updates on this matter.

I have also tried alank's answer from the post modifying my MOSI pin which is currently connected to the output device's SDIO to be kLPSPI_SdoInSdoOut but with no success.

The 1170 driver seems to have some support for half-duplex mode but it only goes as far as setting 0b1 to the config register

DCheung_1-1683084534462.png

 

 

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @DCheung,

For a proper support of half-duplex mode of the LPSPI module, is by setting the correct pin configuration described on Section 70.3.1.4 Pin configuration:
EdwinHz_0-1683235426342.png

Set PINCFG to either '01' or '10': 
EdwinHz_1-1683235509774.png

Set the RXMSK and TXMSK:
EdwinHz_2-1683235646254.png

And set OUTCFG = '1':
EdwinHz_3-1683235818334.png

These are the changes that the post you reference is trying to exemplify. Please make sure you are properly implementing these changes in order for 3 wire operation to work adequately.

BR,
Edwin

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @DCheung,

For a proper support of half-duplex mode of the LPSPI module, is by setting the correct pin configuration described on Section 70.3.1.4 Pin configuration:
EdwinHz_0-1683235426342.png

Set PINCFG to either '01' or '10': 
EdwinHz_1-1683235509774.png

Set the RXMSK and TXMSK:
EdwinHz_2-1683235646254.png

And set OUTCFG = '1':
EdwinHz_3-1683235818334.png

These are the changes that the post you reference is trying to exemplify. Please make sure you are properly implementing these changes in order for 3 wire operation to work adequately.

BR,
Edwin

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DCheung
Contributor II

Hi Edwin,

Thank you for your reply. I believe what you have screen captured makes a lot of sense. I spent a bit more time to understand how the nxp driver attempts to act on half-duplex and I could see that what you have mentioned has mostly been supported by the driver itself. For example,

The driver is aware of setting the Tx/Rx masks when appropriate.

DCheung_0-1683260971473.png

OUTCFG is also being set when it detects 3-wire mode

DCheung_1-1683261031472.png

My code is something like below and the problem I am seeing is that the initial transmit could be clearly seen on an oscilloscope, but with the following receive, only the clock line could be seen and the MOSI line looks like it's fighting control with the master (some ripples in sync with clock near 0V). From what I can see from the nxp driver, all I have to do is to ensure PINCFG is set correctly and the rest is handled by the driver but could still not achieve the result I wanted. Please let me know if you could spot anything odd with my logic.

LPSPI_MasterGetDefaultConfig(&config);

config.pinCfg = kLPSPI_SdoInSdoOut; // This should set PINCFG to '10'

LPSPI_MasterInit(LPSPI3, &config, clock);

lpspi_transfer_t xfer;

xfer.txData = txBuffer;

xfer.rxData = NULL;

LPSPI_MasterTransferNonBlocking(LPSPI3, &handle, &xfer);

// Wait for the transfer to finish ...

xfer.txData = NULL;

xfer.rxData = rxBuffer;

LPSPI_MasterTransferNonBlocking(LPSPI3, &handle, &xfer);

 

 

 

 

 

 

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EdwinHz
NXP TechSupport
NXP TechSupport

What about the status flags on register SPIx_SR? Do you see any flags when experiencing this issue? Are you certain the setup is adequate for your specific slave device(s)?

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DCheung
Contributor II

Seems like the datasheet of the slave device has a terrible SPI diagram using just one data line which made us all thought it was using 3-wire mode. Turns out it's just running normal SPI but the manufacturer decided to use a 3-wire diagram to demonstrate communication. Thanks for the help anyway as I believe the information will be useful for others.