"i.MX 6 Series DDR Calibration" document typo?

[norishinozaki]

Hello,

In the "i.MX 6 Series DDR Calibration" document page 34,

the sample code enables power mode at the end of the calibration.

// enable Adopt power down timer:

reg32_write((MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET),

reg32_read((MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET)) & 0xfffffff7)

This code is trying to unmask bit 3 in MMDC0_MAPSR, however in the RM page 3927, the bit 3 is a reserved bit.

Is it actually 0xfffffffe to set 0 in the bit 0?

Best regards,

Nori Shinozaki

[Yuri]

Hello,

   Looks like the document  "i.MX 6 Series DDR Calibration" and calibration

codes are based on preliminary i.MX6 specs, where bit field MAPSR[3-1] was

defined. Striclty speaking, this field should not be used by applications.

Have a great day,
Yuri

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[norishinozaki]

Hello Yuri,

Thanks, so you mean that setting 0 in the bit 0 is the correct code?

// enable Adopt power down timer:

reg32_write((MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET),

reg32_read((MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET)) & 0xfffffffe)

Best regards,

Nori Shinozaki

[Yuri · Accepted solution]

Yes, the bit 0 is functional and it may be set / cleared, so mask 0xfffffffe

is correct for it.

Regards,

Yuri.

[norishinozaki]

Yuri,

Thanks always!

N.Shinozaki