mx233 interrupt vector table (IVT)

[nidalp]

I was testing some code on mx233 the other day and got "SWI" string printed out on debug uart after which processor reboots.

I guessed that this means some code I linked (newlib 1.20.0) used SWI instruction for something, and ocrom caught it and rebooted processor.

To confirm this I went through ton of documents and little less code from different projects, but got almost nowhere.

This I found in mx233 technical manual:

"

The vector table pointing to these interrupts can be located at physical address 0x00000000 or 0xFFFF0000. The i.MX23 maps its 64-Kbyte on-chip ROM to the address 0xFFFF0000 to 0xFFFFFFFF. The core is hardwired to use the high address vector table at hard reset (core port VINITHI =1).

"

So, is this mapping only hardwired for hard reset or forever?

I'm still trying to find out:

- does mx233 support IVT we can set up from code (looks like mx25 and mx28 do)?

- if it does, how is it done? where is the chip register I should write 1 or 0 to so IVT is remapped to 0x00000000?

- if it doesn't, then what ocrom does with abort, undef, swi and exceptions other than irq and fiq? is there a way to handle those other exceptions?

I realize that I must have compiled newlib so that it uses swi for some of 16 (or was it 18?) syscalls we need to implement, I just don't know which one.

I have implemented them all except 3 (kill, exit and can't remember third). Linker was complaining about already defined functions.

Anyway, back to the topic, question is not about newlib, it is about IVT in mx233. Any ideas?

Tnx.

[JackyAtFreescal · Accepted solution]

ARM926EJ-S Technical Reference Manual has the description for the Control Register c1:

[13] V bit Location of exception vectors:

0 = Normal exception vectors selected, address range = 0x0000 0000 to 0x0000 001C

1 = High exception vectors selected, address range = 0xFFFF 0000 to 0xFFFF 001C.

Set to the value of VINITHI on reset.

So you may change the mapping.

Regards,

Jacky

[nidalp]

Saw that one too, just wasn't clear is it hardwired or just loaded on reset in iMX233.

Thanks!

[OtavioSalvador]

When I were porting U-Boot I have used it properly load SRAM as:

options {

        driveTag = 0x00;

        flags = 0x01;

}

sources {

        u_boot_spl="spl/u-boot-spl.bin";

        u_boot="u-boot.bin";

}

section (0) {

        load u_boot_spl > 0x0000;

        load ivt (entry = 0x0014) > 0x8000;

        call 0x8000;

        load u_boot > 0x40000100;

        call 0x40000100;

}

[architect]

Hello,

I am looking at the u-boot-spl for OLinuXino-MICRO (iMX233) and trying to understand the booting process

Can somebody explain the following command:

     load ivt (entry = 0x0014) > 0x8000;

Why 0x14 and why 0x8000?

Thank you in advance,

Valentin

[nidalp]

Also one of the things I was looking for in elftosb manual:

how to load ivt in 0x00000000 and rest of the binary in SDRAM?

Didn't find anything like "load ivt (entry = 0x0014) > 0x8000;" in the doc but will give it a try definitely!

Thanks!

[OtavioSalvador]

Ah; this was a trick used for the CPU to jump onto the SDRAM.