we use lan8720 phy in imx6q platform through RMII interface.
we config lan8720 to generate 50M ref clock for mac, and connect this 50M clock to ENET_REF_CLK pin.
but according to "IMX6DQ6SDLHDG.pdf", ENET_REF_CLK is not used by the RMII interface and recommend to use GPIO_16 as source pin of 50M clock.
any software workaround can solve our ploblem? we don't want to modify the hardware design.
This is my test code for MX6Q with LAN8720a RMII interface
// ENET
MX6Q_PAD_ENET_MDIO__ENET_MDIO,
MX6Q_PAD_ENET_MDC__ENET_MDC,
/*
(IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT)
Address: 20E_0000h base + 858h offset = 20E_0858h
MUX Mode Select Field
Selecting Pads Involved in Daisy Chain.
Instance: enet, In Pin: ipp_ind_mac0_rxen
bit0:1 ENET_CRS_DV_ALT1 — Selecting ALT1 mode of pad ENET_CRS_DV for ENET_RX_EN.
(IOMUXC_ENET_REF_CLK_SELECT_INPUT)
Address: 20E_0000h base + 83Ch offset = 20E_083Ch
MUX Mode Select Field
Selecting Pads Involved in Daisy Chain.
Instance: enet, In Pin: ipg_clk_rmii
bit0:1 GPIO16_ALT2 — Selecting ALT2 mode of pad GPIO_16 for ENET_REF_CLK.
appiled to the u-boot/board/freescale/mx6q_sabresd/flash_header.S
*/
MX6Q_PAD_ENET_RXD0__ENET_RDATA_0,
MX6Q_PAD_ENET_RXD1__ENET_RDATA_1,
MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN, // ENET_CRS_DV_ALT1
MX6Q_PAD_ENET_TXD0__ENET_TDATA_0,
MX6Q_PAD_ENET_TXD1__ENET_TDATA_1,
MX6Q_PAD_ENET_TX_EN__ENET_TX_EN,
MX6Q_PAD_ENET_RX_ER__ENET_RX_ER,
MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
we modify the hardware connection. it's ok now. thanks for all your helpful answer.
You are right, according to Chapter 11 (Using the RMII Interface) of the Hardware
Development Guide for i.MX6 : "There are two possible pins that can either
source or sink the reference clock: GPIO_16 and RGMII_TX_CTL."
GPIO_16 is intended for RMII reference clock; ENET_REF_CLK is intended for RGMII
reference clock.
I am afraid there is not software solution how external ref clock from ENET_REF_CLK
may be provided for RMII. Sorry.