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[imx8mp] remoteproc0: bad phdr da 0x80... mem 0x2a8

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[imx8mp] remoteproc0: bad phdr da 0x80... mem 0x2a8

‎01-31-2023 02:05 AM
1,631 Views
SegFault0
Contributor II

Hello,

I'm trying to run a hello world example from the MCUXpresso SDK (SDK_2.12.1_MIMX8ML8xxxLZ) on my imx8mp-m7 (OS: 5.15-kirkstone, Kernel: Linux 5.15.52) using the remoteproc framework. For the build, I use the gcc-arm-none-eabi-10-2020-q4-major-win32 release. The hello world example can be differentiated into 3 releases : DDR RAM, flash and RAM. For the flash and DDR RAM release, I get the following error:

 

Spoiler
08:45:31 lec-imx8mp kernel: : mipi_csis_imx8mp_phy_reset, No remote pad found!
08:35:23 lec-imx8mp kernel: remoteproc remoteproc0: powering up imx-rproc
08:35:23 lec-imx8mp kernel: remoteproc remoteproc0: Booting fw image hello_world.elf, size 152740
08:35:23 lec-imx8mp kernel: remoteproc remoteproc0: bad phdr da 0x80000000 mem 0x2a8
08:35:23 lec-imx8mp kernel: remoteproc remoteproc0: Failed to load program segments: -22
08:35:23 lec-imx8mp kernel: remoteproc remoteproc0: Boot failed: -22

 For the RAM release, the whole system freezes.

Memory sections from the ld-script are as following:

 

Spoiler
MEMORY //DDR RAM release
{
  m_interrupts          (RX)  : ORIGIN = 0x80000000, LENGTH = 0x00000400
  m_text                (RX)  : ORIGIN = 0x80000400, LENGTH = 0x001FFC00
  m_data                (RW)  : ORIGIN = 0x80200000, LENGTH = 0x00200000
  m_data2               (RW)  : ORIGIN = 0x80400000, LENGTH = 0x00C00000
}

MEMORY //Flash release
{
  m_interrupts          (RX)  : ORIGIN = 0x08000000, LENGTH = 0x00000400
  m_text                (RX)  : ORIGIN = 0x08000400, LENGTH = 0x000FFC00
  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
  m_data2               (RW)  : ORIGIN = 0x80000000, LENGTH = 0x01000000
  m_tcml                (RW)  : ORIGIN = 0x00000020, LENGTH = 0x0001FFE0
}

MEMORY //RAM release
{
  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
  m_text                (RX)  : ORIGIN = 0x00000400, LENGTH = 0x0001FC00
  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
  m_data2               (RW)  : ORIGIN = 0x80000000, LENGTH = 0x01000000
}

Device tree:

Spoiler
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "../freescale/imx8mp.dtsi"
#include "../freescale/imx8mp-evk.dts"

//#define ENABLE_OV13850 1

/ {
	model = "ADLINK LEC-iMX8MP SOM module";
	compatible = "fsl,imx8mp-evk", "fsl,imx8mp", "adlink,lec-imx8mp";

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		//rpmsg_reserved: rpmsg@0x55800000 {
		//	no-map;
		//	reg = <0 0x55800000 0 0x800000>;
		//};

		m4_reserved: m4@0x80000000 {
			no-map;
			reg = <0 0x80000000 0 0x1000000>;
		};

		vdev0vring0: vdev0vring0@55000000 {
			reg = <0 0x55000000 0 0x8000>;
			no-map;
		};

		vdev0vring1: vdev0vring1@55008000 {
			reg = <0 0x55008000 0 0x8000>;
			no-map;
		};

		vdevbuffer: vdevbuffer@55400000 {
			compatible = "shared-dma-pool";
			reg = <0 0x55400000 0 0x100000>;
			no-map;
		};

		rsc_table: rsc_table@550ff000 {
			reg = <0 0x550ff000 0 0x1000>;
			no-map;
		};

		audio_reserved: audio@0x81000000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0 0x81000000 0 0x10000000>;
		};

		micfil_reserved: mic_rpmsg@91000000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0 0x91000000 0 0x100000>;
		};
	};

	sound-wm8960 {
		status = "disabled";
	};

	sound-micfil {
		status = "disabled";
	};

	rpmsg_audio: rpmsg_audio {
		compatible = "fsl,imx8mp-rpmsg-audio";
		model = "wm8960-audio";
		fsl,platform = "rpmsg-audio-channel";
		fsl,enable-lpa;
		fsl,rpmsg-out;
		fsl,rpmsg-in;
		assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
		assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
		assigned-clock-rates = <12288000>;
		clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>,
			 <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>,
			 <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>,
			 <&clk IMX8MP_AUDIO_PLL1_OUT>,
			 <&clk IMX8MP_AUDIO_PLL2_OUT>;
		clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k";
		audio-codec = <&codec>;
		memory-region = <&audio_reserved>;
		power-domains = <&audiomix_pd>;
		audio-routing =
			"LINPUT1", "MICB",
			"LINPUT3", "MICB";
		status = "okay";
	};

	rpmsg_micfil: rpmsg_micfil {
		compatible = "fsl,imx8mp-rpmsg-audio";
		model = "micfil-audio";
		fsl,platform = "rpmsg-micfil-channel";
		fsl,enable-lpa;
		fsl,rpmsg-in;
		assigned-clocks = <&clk IMX8MP_CLK_PDM>;
		assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
		assigned-clock-rates = <196608000>;
		clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG>,
			 <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT>,
			 <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>,
			 <&clk IMX8MP_AUDIO_PLL1_OUT>,
			 <&clk IMX8MP_AUDIO_PLL2_OUT>;
		clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k";
		memory-region = <&micfil_reserved>;
		power-domains = <&audiomix_pd>;
		status = "okay";
	};

	imx8mp-cm7 {
		compatible = "fsl,imx8mn-cm7";
		rsc-da = <0x55000000>;
		clocks = <&clk IMX8MP_CLK_M7_DIV>;
		mbox-names = "tx", "rx", "rxdb";
		mboxes = <&mu 0 1
			  &mu 1 1
			  &mu 3 1>;
		memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>;
		status = "okay";
		fsl,startup-delay-ms = <500>;
	};



	chosen {
		stdout-path = &uart2;
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_led>;

		status {
			label = "green:status";
			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
			default-state = "on"; /* LED GREEN */
		};
	};

	// gpio1_IO14 on lec-imx8mp is oc pin
	reg_usb1_host_vbus: regulator-usb1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb1_host_vbus";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1_vbus>;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
		off-on-delay-us = <12000>;
	};

	sound-hdmi {
		compatible = "fsl,imx-audio-hdmi";
		model = "audio-hdmi";
		audio-cpu = <&aud2htx>;
		hdmi-out;
		constraint-rate = <44100>,
				<88200>,
				<176400>,
				<32000>,
				<48000>,
				<96000>,
				<192000>;
		status = "okay";
	};

	sound-xcvr {
		compatible = "fsl,imx-audio-card";
		model = "imx-audio-xcvr";
		pri-dai-link {
			link-name = "XCVR PCM";
			cpu {
				sound-dai = <&xcvr>;
			};
		};
	};

	lvds_backlight: lvds_backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm2 0 100000>;
		status = "okay";

		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <80>;
	};

	fixed-regulators {
		compatible = "simple-bus";
		device_type = "fixed-regulators";
		#address-cells = <1>;
		#size-cells = <0>;

		dp83867_2v5: regulator-enet {
			compatible = "regulator-fixed";
			//reg = <13>;
			regulator-name = "enet-2v5";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			gpio = <&gpio7 15 GPIO_ACTIVE_HIGH>;
			regulator-boot-on;
			regulator-always-on;
			enable-active-high;
		};
	};

};

&clk {
	init-on-array = <IMX8MP_CLK_HSIO_ROOT>;
	clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
		 <&clk_ext3>, <&clk_ext4>, <&sai1_mclk>, <&sai2_mclk>,
		 <&sai3_mclk>, <&sai5_mclk>, <&sai6_mclk>, <&sai7_mclk>;
	clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
		      "clk_ext3", "clk_ext4", "sai1_mclk", "sai2_mclk",
		      "sai3_mclk", "sai5_mclk", "sai6_mclk", "sai7_mclk";
	assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
			  <&clk IMX8MP_CLK_A53_CORE>,
			  <&clk IMX8MP_CLK_NOC>,
			  <&clk IMX8MP_CLK_NOC_IO>,
			  <&clk IMX8MP_CLK_GIC>,
			  <&clk IMX8MP_CLK_AUDIO_AHB>,
			  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
			  <&clk IMX8MP_AUDIO_PLL1>,
			  <&clk IMX8MP_AUDIO_PLL2>,
			  <&clk IMX8MP_VIDEO_PLL1>,
			  <&clk IMX8MP_CLK_SAI1>,
			  <&clk IMX8MP_CLK_SAI2>,
			  <&clk IMX8MP_CLK_SAI3>,
			  <&clk IMX8MP_CLK_SAI5>,
			  <&clk IMX8MP_CLK_SAI6>,
			  <&clk IMX8MP_CLK_SAI7>;
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&dsp {
	status = "okay";
};

&aud2htx {
	status = "okay";
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "okay";
};

&ecspi1{
	#address-cells = <1>;
	#size-cells = <0>;
	
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	status = "okay";

	spidev0: spi@0 {
		reg = <0>;
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <500000>;
	};
};

&ecspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "okay";

	spidev1: spi@0 {
		reg = <0>;
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <500000>;
	};
};

/* eth1 */
&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rgmii-id";
	phy-handle = <&dp83867_1>;
	snps,force_thresh_dma_mode;
	snps,mtl-tx-config = <&mtl_tx_setup>;
	snps,mtl-rx-config = <&mtl_rx_setup>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		/* TODO : RESET needed
		 * TODO : IRQ   needed
		 */
		dp83867_1: ethernet-phy@0 {
			/* RGMII-1 */
			compatible = "ethernet-phy-id2000.a231"; 
			reg = <0>;

			ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

			ti,min-output-impedance;
			ti,dp83867-rxctrl-strap-quirk;

			interrupt-parent = <&gpio4>;
			interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
			reset-gpio = <&gpio4 22 GPIO_ACTIVE_LOW>;
		};
	};

	mtl_tx_setup: tx-queues-config {
		snps,tx-queues-to-use = <5>;
		snps,tx-sched-sp;
		queue0 {
			snps,dcb-algorithm;
			snps,priority = <0x1>;
		};
		queue1 {
			snps,dcb-algorithm;
			snps,priority = <0x2>;
		};
		queue2 {
			snps,dcb-algorithm;
			snps,priority = <0x4>;
		};
		queue3 {
			snps,dcb-algorithm;
			snps,priority = <0x8>;
		};
		queue4 {
			snps,dcb-algorithm;
			snps,priority = <0xf0>;
		};
	};
	mtl_rx_setup: rx-queues-config {
		snps,rx-queues-to-use = <5>;
		snps,rx-sched-sp;
		queue0 {
			snps,dcb-algorithm;
			snps,priority = <0x1>;
			snps,map-to-dma-channel = <0>;
		};
		queue1 {
			snps,dcb-algorithm;
			snps,priority = <0x2>;
			snps,map-to-dma-channel = <1>;
		};
		queue2 {
			snps,dcb-algorithm;
			snps,priority = <0x4>;
			snps,map-to-dma-channel = <2>;
		};
		queue3 {
			snps,dcb-algorithm;
			snps,priority = <0x8>;
			snps,map-to-dma-channel = <3>;
		};
		queue4 {
			snps,dcb-algorithm;
			snps,priority = <0xf0>;
			snps,map-to-dma-channel = <4>;
		};
	};
};

/* eth0 */
&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rgmii-id";
	phy-handle = <&dp83867_0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		dp83867_0: ethernet-phy@1 {
			/* RGMII-1 */
			compatible = "ethernet-phy-id2000.a231";

			reg = <1>;

			interrupt-parent = <&gpio4>;
			interrupts =  IRQ_TYPE_EDGE_FALLING>;
			reset-gpio = <&gpio4 4 GPIO_ACTIVE_LOW>;

			ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

			ti,min-output-impedance;
			ti,dp83867-rxctrl-strap-quirk;
		};
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@25 {
		reg = <0x25>;
		compatible = "nxp,pca9450";
		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
		pinctrl-0 = <&pinctrl_pmic>;
		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;

		regulators {
			#address-cells = <1>;
			#size-cells = <0>;

			pca9450,pmic-buck2-uses-i2c-dvs;
			/* Run/Standby voltage */
			pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;

			buck1_reg: regulator@0 {
				reg = <0>;
				regulator-compatible = "buck1";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck2_reg: regulator@1 {
				reg = <1>;
				regulator-compatible = "buck2";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck4_reg: regulator@3 {
				reg = <3>;
				regulator-compatible = "buck4";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5_reg: regulator@4 {
				reg = <4>;
				regulator-compatible = "buck5";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6_reg: regulator@5 {
				reg = <5>;
				regulator-compatible = "buck6";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: regulator@6 {
				reg = <6>;
				regulator-compatible = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2_reg: regulator@7 {
				reg = <7>;
				regulator-compatible = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_reg: regulator@8 {
				reg = <8>;
				regulator-compatible = "ldo3";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4_reg: regulator@9 {
				reg = <9>;
				regulator-compatible = "ldo4";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo5_reg: regulator@10 {
				reg = <10>;
				regulator-compatible = "ldo5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	codec: wm8960@1a {
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>;
		clock-names = "mclk";
		wlf,shared-lrclk;
		status="okay";
	};

	/* SX1509(2) U1001@IPi SMARC Plus */
	gpio8: i2c2_gpioext0@3e {
		/* GPIO Expander 2 Mapping :
		 * - 0: E_GPIO1_0	<=>					IPi SMARC Plus CN101_PIN29: E_GPIO1_0
		 * - 1: E_GPIO1_1	<=>					IPi SMARC Plus CN101_PIN31: E_GPIO1_1
		 * - 2: E_GPIO1_2	<=>					IPi SMARC Plus CN101_PIN32: E_GPIO1_2
		 * - 3: E_GPIO1_3	<=>					IPi SMARC Plus CN101_PIN33: E_GPIO1_3
		 * - 4: E_GPIO1_4	<=>					IPi SMARC Plus CN101_PIN35: E_GPIO1_4
		 * - 5: E_GPIO1_5	<=>					IPi SMARC Plus CN101_PIN36: E_GPIO1_5
		 * - 6: E_GPIO1_6	<=>					IPi SMARC Plus CN101_PIN37: E_GPIO1_6
		 * - 7: E_GPIO1_7	<=>					IPi SMARC Plus CN101_PIN38: E_GPIO1_7
		 * - 8: E_GPIO2_8	<=>					IPi SMARC Plus CN101_PIN40: E_GPIO2_8
		 * - 9: TP1002		<=>					IPi SMARC Plus TP1002 (won't use)
		 * - 10: TP1003		<=>					IPi SMARC Plus TP1003 (won't use)
		 * - 11: TP1004		<=>					IPi SMARC Plus TP1004 (won't use)
		 * - 12: TP1005		<=>					IPi SMARC Plus TP1005 (won't use)
		 * - 13: TP1006		<=>					IPi SMARC Plus TP1006 (won't use)
		 * - 14: TP1007		<=>					IPi SMARC Plus TP1007 (won't use)
		 * - 15: TP1008		<=>					IPi SMARC Plus TP1008 (won't use)
		 * - 16: OSCIO		<=>					IPi SMARC Plus TP1001 (won't use)
		 */
		#gpio-cells = <2>;
		#interrupt-cells = <2>;
		compatible = "semtech,sx1509q";
		reg = <0x3e>;

		semtech,probe-reset;
		gpio-controller;
		interrupt-controller;

		interrupt-parent = <&gpio6>;
		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
	};
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	/* TODO : Camera(0) device */
	ov5640_0: ov5640_mipi@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>;
		clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
		clock-names = "xclk";
		assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
		assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
		assigned-clock-rates = <24000000>;
		csi_id = <0>;
		powerdown-gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
		mclk = <24000000>;
		mclk_source = <0>;
		mipi_csi;
		status = "okay";

		port {
			ov5640_mipi_0_ep: endpoint {
				remote-endpoint = <&mipi_csi0_ep>;
				data-lanes = <1 2>;
                                clock-lanes = <0>;
			};
		};
	};
};

&i2c5 {
	#address-cells = <1>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c5>;
	status = "okay";

#ifdef ENABLE_OV13850
	ov13850_mipi: ov13850_mipi@10  {
		compatible = "ov13850_mipi";
		reg = <0x10>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>;
		mclk = <24000000>;
		mclk_source = <0>;
		clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
		clock-names = "csi_mclk";
		assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
		assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
		assigned-clock-rates = <24000000>;

		pwn-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
		rst-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
		virtual_channel = <0>;
		mipi_csi;

		port@0 {
			ov13850_mipi_1_ep: endpoint {
				remote-endpoint = <&mipi_csi1_ep>;
			};
		};
	};
#else
	ov13855_mipi: ov13855_mipi@36 {
		compatible = "ov13855_mipi";
		reg = <0x36>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>;
		mclk = <24000000>;
		mclk_source = <0>;
		clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
		clock-names = "csi_mclk";
		assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
		assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
		assigned-clock-rates = <24000000>;

		pwn-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
		rst-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
		virtual_channel = <0>;
		mipi_csi;

		port@0 {
			ov13855_mipi_1_ep: endpoint {
				remote-endpoint = <&mipi_csi1_ep>;
			};
		};
	};
#endif
};

&i2c6{
	#address-cells = <1>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c6>;
	status = "okay";

	/* TPM - ST33TPHF2XI2C U2301 */
	st33tphf2xi2c@2e {
		#gpio-cells = <2>;
		#interrupt-cells = <2>;
		compatible = "st,st33htpm-i2c";
		reg = <0x2e>;

		label = "tpm";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c6_tpm_irq &pinctrl_tpm>;
		interrupt-parent = <&gpio3>;
		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
		reset-gpio = <&gpio6 11 GPIO_ACTIVE_LOW>;
		status = "okay";
	};

	/* SX1509(0) U2605 */
	gpio6: i2c6_gpioext0@3f {
		/* GPIO Expander 0 Mapping :
		 * - 0: CN_GPIO4		<=>				SMARC GPIO4/HDA_RST_N	<=> IPi SMARC Plus CN1701_PIN02:	HDA_RST_N_3V (in) (won't use)
		 * - 1: CN_GPIO5		<=>				SMARC GPIO5/PWM_OUT		<=> IPi SMARC Plus U1001:			Semtech_SX1509B: I2C_ALERT_N (in)
		 * - 2: CN_GPIO6		<=>				SMARC GPIO6/TACHIN		<=> IPi SMARC Plus CN1001_PIN07:	S_GPIO06_3V
		 * - 3: CN_GPIO7		<=>				SMARC GPIO7				<=> IPi SMARC Plus CN1001_PIN12:	S_GPIO07_3V
		 * - 4: CN_GPIO8		<=>				SMARC GPIO8				<=> IPi SMARC Plus CN1001_PIN11:	S_GPIO08_3V 
		 * - 5: CN_GPIO9		<=>				SMARC GPIO9				<=> IPi SMARC Plus CN1001_PIN13:	S_GPIO09_3V
		 * - 6: CN_GPIO10		<=>				SMARC GPIO10			<=> IPi SMARC Plus CN1001_PIN15:	S_GPIO10_3V
		 * - 7: CN_GPIO11		<=>				SMARC GPIO11			<=> IPi SMARC Plus CN1001_PIN16:	S_GPIO11_3V
		 * - 8: CN_GPIO12		<=>				SMARC GPIO12			<=> IPi SMARC Plus CN1001_PIN18:	S_GPIO12_3V (external pull high 3V)
		 * - 9: CN_GPIO13		<=>				SMARC GPIO13			<=> IPi SMARC Plus CN1001_PIN22:	S_GPIO13_3V (external pull high 3V)
		 * - 10: BT_DEV_WAKE	<= R2214(NI) => U2201	AazureWave AW-CM276NF ATEST0
		 * - 11: TPM_RST_N		<=>				U2301	ST ST33HTPH2X32AHD5 RESET_N (out low / pull-high)
		 * - 12: WIFI_BT_3V3_EN	<= PR2201 =>	PU2201	TI TPS82085SILR EN(out high)
		 * - 13: M2_BT_WAKE_DEV	<=>				U2201	AazureWave AW-CM276NF GPIO12/UART_Host_Wake_BT#
		 * - 14: REBOOT_COUNT	<= R1130 =>		U1101	ST STM32L071RBH6TR REBOOT_COUNT_BMC (out high)
		 * - 15: BT_REG_ON		<= R2215(NC) =>	U2201	AazureWave AW-CM276NF GPIO22/PCIE_W_DISABLE#
		 * - 16: OSCIO			<=>				TP2601 (won't use)
		 */
		#gpio-cells = <2>;
		#interrupt-cells = <2>;
		compatible = "semtech,sx1509q";
		reg = <0x3f>;

		semtech,probe-reset;
		gpio-controller;
		interrupt-controller;

		interrupt-parent = <&gpio1>;
		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
	};

	/* SX1509(1) U2606 */
	gpio7: i2c6_gpioext1@70 {
		/* GPIO Expander 1 Mapping :
		 * - 0: SLEEP-L			<=				SMARC SLEEP# (won't use)
		 * - 1: CHARGING-L		<=				SMARC CHARGING# (won't use)
		 * - 2: CHARGER_PRSNT-L	<=				SMARC CHARGER_PRSNT# (won't use)
		 * - 3: BATLOW-L		<=				SMARC BATLOW# (won't use)
		 * - 4: HWID-3			<= R2640 		GND (in)
		 * - 5: GPIOE_1			<= R2638 		GND (in)
		 * - 6: TPM_PP			 =>				U2301	ST ST33HTPH2X32AHD5 GPIO_PP (out high)
		 * - 7: TPM_LP			 =>				U2301	ST ST33HTPH2X32AHD5 GPIO_LP (out high)
		 * - 8: HWID_1			<= R2629 		GND (in)
		 * - 9: HWID_2			<= R2628 		GND (in)
		 * - 10: BOMID_1		<= R2632 		GND (in)
		 * - 11: BOMID_2		<= R2631 		GND (in)
		 * - 12: BOMID_3		<= R2630 		GND (in)
		 * - 13: TEST-L			<= R1146(NI) =>	U1101	ST STM32L071RBH6TR TEST-L_BMC (won't use)
		 * - 14: SMB_ALERT_N	<=				SMARC SMB_ALERT_1V8# (won't use)
		 * - 15: VDD_2V5_ENT_EN	   PR910 =>		PU901 TI TPS74801DRCR EN (out active high to turn on U1501 DP83867IRRGZR)
		 * - 16: OSCIO			<=>				TP2602 (won't use)
		 */
		#gpio-cells = <2>;
		#interrupt-cells = <2>;
		compatible = "semtech,sx1509q";
		reg = <0x70>;

		semtech,probe-reset;
		gpio-controller;
		interrupt-controller;

		interrupt-parent = <&gpio4>;
		interrupts = <19 IRQ_TYPE_EDGE_FALLING>;

		pinctrl_tpm: tpmgrp {
			pins = "gpio6","gpio7"; // TPM_PP, TPM_LP
			output-high;
		};
	};

	/* RTC U2607 */
	pcf8563: rtc@51 {
		compatible = "nxp,pcf8563";
		reg = <0x51>;
		#clock-cells = <0>;
	};

	/* Lite-BMC U1101*/
	adl-bmc@28 {
		compatible = "adl-bmc";
		reg = <0x28>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&pcf8563>;
	};
};

&irqsteer_hdmi {
	status = "okay";
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "okay";
};

&hdmi_blk_ctrl {
	status = "okay";
};

&hdmi_pavi {
	status = "okay";
};

&hdmi {
	status = "okay";
};

&hdmiphy {
	status = "okay";
};

&lcdif1 {
	status = "okay";
};

&lcdif2 {
	status = "okay";
};

&lcdif3 {
	status = "okay";

	thres-low  = <1 2>;	/* (FIFO * 1 / 2) */
	thres-high =  4>;	/* (FIFO * 3 / 4) */
};

&ldb {
	status = "disabled";
};

&ldb_phy {
	status = "disabled";
};

&mipi_dsi {
	status = "disabled";
};

&snvs_pwrkey {
	status = "okay";
};

&easrc {
	fsl,asrc-rate  = <48000>;
	status = "okay";
};

&micfil {
	status = "disabled";
};

&pcie{
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio4 20 GPIO_ACTIVE_LOW>;
	ext_osc = <0>;
	clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>,
		 <&clk IMX8MP_CLK_PCIE_AUX>,
		 <&clk IMX8MP_CLK_PCIE_ROOT>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>,
			  <&clk IMX8MP_CLK_PCIE_AUX>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
				 <&clk IMX8MP_SYS_PLL2_50M>;
	//reserved-region = <&rpmsg_reserved>;
	fsl,tx-deemph-gen1 = <0x1f>;
	status = "disabled"; // okay
};

&pcie_ep{
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	ext_osc = <1>;
	clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>,
		 <&clk IMX8MP_CLK_PCIE_AUX>,
		 <&clk IMX8MP_CLK_PCIE_ROOT>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>,
			  <&clk IMX8MP_CLK_PCIE_AUX>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
				 <&clk IMX8MP_SYS_PLL2_50M>;
	status = "disabled";
};

&pcie_phy{
	clock-names = "phy";
	assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
	ext_osc = <1>;
	status = "okay";
};

&sai2 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <12288000>;
	status = "okay";
};

&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <12288000>;
	clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
		 <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
		 <&clk IMX8MP_CLK_DUMMY>;
	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
	fsl,sai-mclk-direction-output;
	status = "okay";
};

&xcvr {
	#sound-dai-cells = <0>;
	status = "okay";
};

&sdma2 {
	status = "okay";
};

&uart1 { /* BT */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&uart2 {
	/* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	assigned-clocks = <&clk IMX8MP_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	assigned-clocks = <&clk IMX8MP_CLK_UART4>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&usb3_phy0 {
	fsl,phy-tx-vref-tune = <6>;
	fsl,phy-tx-rise-tune = <0>;
	fsl,phy-tx-preemp-amp-tune = <3>;
	fsl,phy-comp-dis-tune = <7>;
	fsl,pcs-tx-deemph-3p5db = <0x21>;
	fsl,phy-pcs-tx-swing-full = <0x7f>;
	status = "okay";
};

&usb3_0 {
	status = "okay";
};

&usb_dwc3_0 {
	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	adp-disable;
	usb-role-switch;
	role-switch-default-mode = "peripheral";
	snps,dis-u1-entry-quirk;
	snps,dis-u2-entry-quirk;
	status = "okay";

	port {
		usb3_drd_sw: endpoint {
			// remote-endpoint = <&typec_dr_sw>;
		};
	};
};

&usb3_phy1 {
	fsl,phy-tx-preemp-amp-tune = <2>;
	status = "okay";
};

&usb3_1 {
	status = "okay";
};

&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <4>;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	bus-width = <4>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3
			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000019
			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x40000019
		>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT	0x116
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT	0x116
		>;
	};

	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x82
			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x82
			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x82
		>;
	};

	pinctrl_ecspi1_cs: ecspi1cs {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40000
		>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82
			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82
			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82
		>;
	};

	pinctrl_ecspi2_cs: ecspi2cs {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40000
		>;
	};

	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x19
		>;
	};

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX          0x154
			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX          0x154
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX		0x154
			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154
		>;
	};

	pinctrl_gpio_lid: gpiolidgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05	0x154	/* LID-L */
		>;
	};	

	pinctrl_gpio_led: gpioledgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c3
			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c3
			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c3
		>;
	};

	pinctrl_i2c5: i2c5grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL		0x400001c3  // value need to re-check
			MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA		0x400001c3  // value need to re-check
		>;
	};

	pinctrl_i2c6: i2c6grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL		0x400001c3  // value need to re-check
			MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA			0x400001c3  // value need to re-check
		>;
	};

	pinctrl_mipi_dsi_en: mipi_dsi_en {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00	0x16
		>;
	};

	pinctrl_pcie: pciegrp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B		0x61 /* open drain, pull up */
			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20		0x41 /* RST  : MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 */
		>;
	};

	pinctrl_pmic: pmicirq {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x41
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC	0xd6
			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK	0xd6
			MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00	0xd6
			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00	0xd6
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6
			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6
			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6
			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6
			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0xd6
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS	0x140
			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS	0x140
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49
			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49
			MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS	0x49
			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS	0x49
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX	0x140
			MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX	0x140
		>;
	};

	pinctrl_uart4: uart4grp {
			fsl,pins = <
			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140
			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140
			MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS	0x140
			MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS	0x140
		>;
	};

	/* TODO : USB OC ON LEC-IMX8MP */
	pinctrl_usb1_vbus: usb1grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x19
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2grp-gpio {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 	0x1c4
			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6
		>;
	};

	pinctrl_csi0_pwn: csi0_pwn_grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x19
		>;
	};

	pinctrl_csi0_rst: csi0_rst_grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x19
		>;
	};

	pinctrl_csi_mclk: csi_mclk_grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2	0x59
		>;
	};

	pinctrl_csi1_pwn: cam1resetgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07		0xd6
		>;
	};

	pinctrl_csi1_rst: csi1_rst_grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x19
		>;
	};

	pinctrl_lvds_pwr_en: lvdspwrengrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0xd6
		>;
	};

	pinctrl_lcd0_vdd_en: lcd0vddengrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0xd6
		>;
	};

	pinctrl_lcd1_vdd_en: lcd1vddengrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0xd6
		>;
	};

	/* IO Expander - 1 IRQ */
	pinctrl_egpio1_int: egpio1intgrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0xd6
		>;
	};

	pinctrl_m2_sd_wake: m2sdwakegrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0xd6
		>;
	};

	pinctrl_m2_bt_wake: m2sdwakegrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0xd6
		>;
	};

	pinctrl_pcie_wake_1v8: pciewake1v8grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0xd6
		>;
	};

	pinctrl_i2c6_tpm_irq: i2c6tpmirqgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0xd6
		>;
	};

	pinctrl_i2c6_rtc_irq: i2c6rtcirqgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22		0xd6
		>;
	};

	pinctrl_disp_select: dispselectgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0xd6
		>;
	};
};

&vpu_g1 {
	status = "okay";
};

&vpu_g2 {
	status = "okay";
};

&vpu_vc8000e {
	status = "okay";
};

&gpu_3d {
	status = "okay";
};

&gpu_2d {
	status = "okay";
};

&ml_vipsi {
	status = "okay";
};

&mix_gpu_ml {
	status = "okay";
};

&mipi_csi_0 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	port@0 {
		reg = <0>;
		mipi_csi0_ep: endpoint {
			remote-endpoint = <&ov5640_mipi_0_ep>;
			data-lanes = <2>;
			csis-hs-settle = <13>;
			csis-clk-settle = <2>;
			csis-wclk;
		};
	};
};

&mipi_csi_1 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	port@1 {
		reg = <1>;
#ifdef ENABLE_OV13850
		mipi_csi1_ep: endpoint {
			remote-endpoint = <&ov13850_mipi_1_ep>;
			data-lanes = <4>;
			csis-hs-settle = <13>;
			/*csis-clk-settle = <2>;*/
			csis-wclk;
		};
#else
		mipi_csi1_ep: endpoint {
			remote-endpoint = <&ov13855_mipi_1_ep>;
			data-lanes = <4>;
			csis-hs-settle = <13>;
			/*csis-clk-settle = <2>;*/
			csis-wclk;
		};
#endif
	};
};

&cameradev {
	status = "okay";
};

&isi_0 {
	status = "okay";
	interface =  0 2>;

	cap_device {
		status = "okay";
	};

	m2m_device {
		status = "okay";
	};
};

&isi_1 {
	status = "okay";
	interface = <2 0 2>;

	cap_device {
		status = "okay";
	};

	m2m_device {
		status = "okay";
	};
};

&dsp {
	status = "okay";
};

&vpu_v4l2 {
       status = "okay";
};

 

 

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2 Replies

‎01-31-2023 04:34 PM
1,605 Views
AldoG
NXP TechSupport
NXP TechSupport

Hello,

Have you followed AN5317?
https://www.nxp.com/docs/en/application-note/AN5317.pdf

There is described the modifications needed to device tree for memory reservation. Also, please note that for i.MX 8M platforms, the root clock for M7/M4 must be kept always enabled by Linux to load the firmware code and start Cortex M7/M4.

By default, NXP Linux BSP keeps the root clock enabled for the M core when it is started from U-Boot. Otherwise, if you need to firstly start the M core from the Linux booting phase, the clock driver (drivers/clk/imx/clk-composite-8m.c) must be updated to always skip the gate registration to keep the root clock always enabled for the M core.

Best regards,
Aldo.

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‎02-01-2023 02:18 AM
1,594 Views
kef2
Senior Contributor V
  • if you need to firstly start the M core from the Linux booting phase, the clock driver (drivers/clk/imx/clk-composite-8m.c) must be updated to always skip the gate registration to keep the root clock always enabled for the M core.

imx_rproc.c driver can be told in device tree to enable specific clock. 

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