imx6solo and LPDDR2 Stress Testing

[deepaktajanpure]

Hi, I want to do LPDDR2 Stress testing on imx6solo custom board. So will you please provide .inc file or any other utility for doing this. DDR Used is MT42L16M32D1HE-18

[pengyong_zhang]

hi @deepaktajanpure 

FIrstly, You do not need to modify the RPA .inc file. Just set the right DDR parameter is OK.

And the RPA file  thay i have sened to you is no issue follow your DDR type. So please check your DDR layout is no problem.

B.R

[pengyong_zhang]

hi, @deepaktajanpure 

what do you mean enable chip select? what is your each step?

[deepaktajanpure]

I just enabled CS0 using below line

setmem /32 0x021b0000 = 0x82010000 // MMDC0_MDCTL

which was not there in your previous script

[pengyong_zhang]

Hi, @deepaktajanpure 

What so you mean not enabled any chip select? you can see the RPA file.

[deepaktajanpure]

After enabling Chip Select I'm getting same error as I posted below. Calibration fails again

[pengyong_zhang]

hi, @deepaktajanpure 

PLease use the attachment file, And also check your PCB design if is folllowing the HDG file.

[deepaktajanpure]

Hi,

Can you please share schematic for imx6solo and lpddr2 part only? We are also designing a board and running a script but we are not successful. If you share the schematic and script then that will be great help.

[deepaktajanpure]

But you have not enabled any chip select in this script. Will you please check it again?

[pengyong_zhang]

hi @deepaktajanpure 

Please choose the default setting of ARM Speed and the attachment file try. 

B.R

[deepaktajanpure]

Still calibration is failing. Please go through below logs and inc file attached herewith

============================================
        DDR Stress Test (2.4.0) 
        Build: Mar  7 2016, 11:17:32
        Freescale Semiconductor, Inc.
============================================

============================================
        Chip ID
CHIP ID = i.MX6 Solo/DualLite (0x61)
Internal Revision = TO1.4
============================================

============================================
        Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00008000
SRC_SBMR2(0x020d801c) = 0x21000001
============================================

ARM Clock set to 800MHz

============================================
        DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is LPDDR2 in 1-channel mode.
Data width: 32, bank num: 4
Row size: 13, col size: 9
Chip select CSD0 is used 
Density per chip select: 64MB 
Density per channel: 64MB 
============================================

Current Temperature: 35
============================================

DDR Freq: 297 MHz

Note: Array result[] holds the DRAM test result of each byte.  
      0: test pass.  1: test fail  
      4 bits respresent the result of 1 byte.    
      result 0001:byte 0 fail. 
      result 0011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000  result[00]=0x1111
ABS_OFFSET=0x04040404  result[01]=0x1111
ABS_OFFSET=0x08080808  result[02]=0x1111
ABS_OFFSET=0x0C0C0C0C  result[03]=0x1111
ABS_OFFSET=0x10101010  result[04]=0x1111
ABS_OFFSET=0x14141414  result[05]=0x1111
ABS_OFFSET=0x18181818  result[06]=0x0010
ABS_OFFSET=0x1C1C1C1C  result[07]=0x0010
ABS_OFFSET=0x20202020  result[08]=0x0010
ABS_OFFSET=0x24242424  result[09]=0x0010
ABS_OFFSET=0x28282828  result[0A]=0x0010
ABS_OFFSET=0x2C2C2C2C  result[0B]=0x0010
ABS_OFFSET=0x30303030  result[0C]=0x0010
ABS_OFFSET=0x34343434  result[0D]=0x0010
ABS_OFFSET=0x38383838  result[0E]=0x0010
ABS_OFFSET=0x3C3C3C3C  result[0F]=0x0010
ABS_OFFSET=0x40404040  result[10]=0x0010
ABS_OFFSET=0x44444444  result[11]=0x0010
ABS_OFFSET=0x48484848  result[12]=0x0010
ABS_OFFSET=0x4C4C4C4C  result[13]=0x0010
ABS_OFFSET=0x50505050  result[14]=0x0010
ABS_OFFSET=0x54545454  result[15]=0x0010
ABS_OFFSET=0x58585858  result[16]=0x0010
ABS_OFFSET=0x5C5C5C5C  result[17]=0x0010
ABS_OFFSET=0x60606060  result[18]=0x1010
ABS_OFFSET=0x64646464  result[19]=0x1111
ABS_OFFSET=0x68686868  result[1A]=0x1111
ABS_OFFSET=0x6C6C6C6C  result[1B]=0x1111
ABS_OFFSET=0x70707070  result[1C]=0x1111
ABS_OFFSET=0x74747474  result[1D]=0x1111
ABS_OFFSET=0x78787878  result[1E]=0x1111
ABS_OFFSET=0x7C7C7C7C  result[1F]=0x1111

Byte 0: (0x18 - 0x60), middle value:0x3c
ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.

Error: failed during ddr calibration

[pengyong_zhang]

hi @deepaktajanpure 

Use the attachment file test again.

[deepaktajanpure]

Hi

your excel sheet is for imx6sx. Excel sheet version is older v1.1, we are using 1.4. sheet is defined for different LPDDR part number (MT42L256M32D2) ours is MT42L16M32D1HE

[pengyong_zhang]

hi, @deepaktajanpure 

Please share your ddr tool setting windows.

[pengyong_zhang]

HI @deepaktajanpure 

Please use the attachment test.

[deepaktajanpure]

Hi, executed file sent by you, but still same problem. It is getting stucked in calibration. Please see the logs shown below

============================================
DDR Stress Test (3.0.0)
Build: Dec 14 2018, 14:12:28
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 Solo/DualLite (0x61)
Internal Revision = TO1.4
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00008000
SRC_SBMR2(0x020d801c) = 0x21000001
============================================

ARM Clock set to 1GHz

============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is LPDDR2 in 1-channel mode.
Data width: 32, bank num: 4
Row size: 13, col size: 9
No chip select is enabled
Density per chip select: 64MB
Density per channel: 64MB
============================================

Current Temperature: 49
============================================

DDR Freq: 396 MHz

[pengyong_zhang]

please share your fail log file.

[deepaktajanpure]

When we click on Calibration it is getting hang. Please see DDR Stress Tester snapshot and log file attached herewith

[pengyong_zhang]

Please use the following setting:

[deepaktajanpure]

Thanks for your reply. Already done the changes you have mentioned, but still not working. Is there anything left?

[pengyong_zhang]

hi, @deepaktajanpure 

Sure, please share your DDR Datasheet.

B.R