imx6q fails to boot from sd4 and spi

[lixuhui112]

My custom board: reference mx6q_sabreauto  BSP: 4.1.15_1.0.0_ga , I can use mfg boot uboot ,but I use sd boot form uSDHC4 and ecspi1,but it not success ，we use  ddr test tool create new calibration settings and  rebuild uboot

 
============================================  
        DDR Stress Test (2.5.2)   
        Build: Mar 31 2016, 23:07:26  
        Freescale Semiconductor, Inc.  
============================================  
 
============================================  
        Chip ID  
CHIP ID = i.MX6 Dual/Quad (0x63)  
Internal Revision = TO1.5  
============================================  
 
============================================  
        Boot Configuration  
SRC_SBMR1(0x020d8004) = 0x00000001  
SRC_SBMR2(0x020d801c) = 0x31000001  
============================================  
 
ARM Clock set to 1GHz  
 
============================================  
        DDR configuration  
BOOT_CFG3[5-4]: 0x00, Single DDR channel.  
DDR type is DDR3   
Data width: 32, bank num: 8  
Row size: 15, col size: 10  
Chip select CSD0 is used   
Density per chip select: 1024MB   
============================================  
 
Current Temperature: 53  
============================================  
 
DDR Freq: 297 MHz   
 
ddr_mr1=0x00000000  
Start write leveling calibration...  
running Write level HW calibration  
Write leveling calibration completed, update the following registers in your initialization script  
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F0023  
    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002B001F  
Write DQS delay result:  
   Write DQS0 delay: 35/256 CK  
   Write DQS1 delay: 31/256 CK  
   Write DQS2 delay: 31/256 CK  
   Write DQS3 delay: 43/256 CK  
 
 
WARNING: write-leveling calibration value is greater than 1/8 CK.  
    Per the reference manual, WALAT must be set to 1 in the register MDMISC(0x021B0018).  
    This has been performed automatically.   
    However, in addition to updating the calibration values in your DDR initialization,   
    it is also REQUIRED change the value of MDMISC in their DDR initialization as follows:   
 
    MMDC_MDMISC (0x021b0018) =  0x00011740  
 
Starting DQS gating calibration  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   
 
BYTE 0:   
    Start:         HC=0x01 ABS=0x00  
    End:         HC=0x02 ABS=0x5C  
    Mean:         HC=0x01 ABS=0x6D  
    End-0.5*tCK:     HC=0x01 ABS=0x5C  
    Final:         HC=0x01 ABS=0x6D  
BYTE 1:   
    Start:         HC=0x00 ABS=0x78  
    End:         HC=0x02 ABS=0x54  
    Mean:         HC=0x01 ABS=0x66  
    End-0.5*tCK:     HC=0x01 ABS=0x54  
    Final:         HC=0x01 ABS=0x66  
BYTE 2:   
    Start:         HC=0x01 ABS=0x00  
    End:         HC=0x02 ABS=0x58  
    Mean:         HC=0x01 ABS=0x6B  
    End-0.5*tCK:     HC=0x01 ABS=0x58  
    Final:         HC=0x01 ABS=0x6B  
BYTE 3:   
    Start:         HC=0x01 ABS=0x00  
    End:         HC=0x02 ABS=0x5C  
    Mean:         HC=0x01 ABS=0x6D  
    End-0.5*tCK:     HC=0x01 ABS=0x5C  
    Final:         HC=0x01 ABS=0x6D  
 
DQS calibration MMDC0 MPDGCTRL0 = 0x4166016D, MPDGCTRL1 = 0x016D016B  
 
Note: Array result[] holds the DRAM test result of each byte.    
      0: test pass.  1: test fail    
      4 bits respresent the result of 1 byte.      
      result 0001:byte 0 fail.   
      result 0011:byte 0, 1 fail.   
 
Starting Read calibration...  
 
ABS_OFFSET=0x00000000    result[00]=0x1111  
ABS_OFFSET=0x04040404    result[01]=0x1111  
ABS_OFFSET=0x08080808    result[02]=0x1011  
ABS_OFFSET=0x0C0C0C0C    result[03]=0x1000  
ABS_OFFSET=0x10101010    result[04]=0x0000  
ABS_OFFSET=0x14141414    result[05]=0x0000  
ABS_OFFSET=0x18181818    result[06]=0x0000  
ABS_OFFSET=0x1C1C1C1C    result[07]=0x0000  
ABS_OFFSET=0x20202020    result[08]=0x0000  
ABS_OFFSET=0x24242424    result[09]=0x0000  
ABS_OFFSET=0x28282828    result[0A]=0x0000  
ABS_OFFSET=0x2C2C2C2C    result[0B]=0x0000  
ABS_OFFSET=0x30303030    result[0C]=0x0000  
ABS_OFFSET=0x34343434    result[0D]=0x0000  
ABS_OFFSET=0x38383838    result[0E]=0x0000  
ABS_OFFSET=0x3C3C3C3C    result[0F]=0x0000  
ABS_OFFSET=0x40404040    result[10]=0x0000  
ABS_OFFSET=0x44444444    result[11]=0x0000  
ABS_OFFSET=0x48484848    result[12]=0x0000  
ABS_OFFSET=0x4C4C4C4C    result[13]=0x0100  
ABS_OFFSET=0x50505050    result[14]=0x0111  
ABS_OFFSET=0x54545454    result[15]=0x1111  
ABS_OFFSET=0x58585858    result[16]=0x1111  
ABS_OFFSET=0x5C5C5C5C    result[17]=0x1111  
ABS_OFFSET=0x60606060    result[18]=0x1111  
ABS_OFFSET=0x64646464    result[19]=0x1111  
ABS_OFFSET=0x68686868    result[1A]=0x1111  
ABS_OFFSET=0x6C6C6C6C    result[1B]=0x1111  
ABS_OFFSET=0x70707070    result[1C]=0x1111  
ABS_OFFSET=0x74747474    result[1D]=0x1111  
ABS_OFFSET=0x78787878    result[1E]=0x1111  
ABS_OFFSET=0x7C7C7C7C    result[1F]=0x1111  
 
Byte 0: (0x0c - 0x4c), middle value:0x2c  
Byte 1: (0x0c - 0x4c), middle value:0x2c  
Byte 2: (0x08 - 0x48), middle value:0x28  
Byte 3: (0x10 - 0x50), middle value:0x30  
 
MMDC0 MPRDDLCTL = 0x30282C2C  
 
Starting Write calibration...  
 
ABS_OFFSET=0x00000000    result[00]=0x1111  
ABS_OFFSET=0x04040404    result[01]=0x1110  
ABS_OFFSET=0x08080808    result[02]=0x0000  
ABS_OFFSET=0x0C0C0C0C    result[03]=0x0000  
ABS_OFFSET=0x10101010    result[04]=0x0000  
ABS_OFFSET=0x14141414    result[05]=0x0000  
ABS_OFFSET=0x18181818    result[06]=0x0000  
ABS_OFFSET=0x1C1C1C1C    result[07]=0x0000  
ABS_OFFSET=0x20202020    result[08]=0x0000  
ABS_OFFSET=0x24242424    result[09]=0x0000  
ABS_OFFSET=0x28282828    result[0A]=0x0000  
ABS_OFFSET=0x2C2C2C2C    result[0B]=0x0000  
ABS_OFFSET=0x30303030    result[0C]=0x0000  
ABS_OFFSET=0x34343434    result[0D]=0x0000  
ABS_OFFSET=0x38383838    result[0E]=0x0000  
ABS_OFFSET=0x3C3C3C3C    result[0F]=0x0000  
ABS_OFFSET=0x40404040    result[10]=0x0000  
ABS_OFFSET=0x44444444    result[11]=0x0000  
ABS_OFFSET=0x48484848    result[12]=0x0000  
ABS_OFFSET=0x4C4C4C4C    result[13]=0x0001  
ABS_OFFSET=0x50505050    result[14]=0x1101  
ABS_OFFSET=0x54545454    result[15]=0x1111  
ABS_OFFSET=0x58585858    result[16]=0x1111  
ABS_OFFSET=0x5C5C5C5C    result[17]=0x1111  
ABS_OFFSET=0x60606060    result[18]=0x1111  
ABS_OFFSET=0x64646464    result[19]=0x1111  
ABS_OFFSET=0x68686868    result[1A]=0x1111  
ABS_OFFSET=0x6C6C6C6C    result[1B]=0x1111  
ABS_OFFSET=0x70707070    result[1C]=0x1111  
ABS_OFFSET=0x74747474    result[1D]=0x1111  
ABS_OFFSET=0x78787878    result[1E]=0x1111  
ABS_OFFSET=0x7C7C7C7C    result[1F]=0x1111  
 
Byte 0: (0x04 - 0x48), middle value:0x26  
Byte 1: (0x08 - 0x50), middle value:0x2c  
Byte 2: (0x08 - 0x4c), middle value:0x2a  
Byte 3: (0x08 - 0x4c), middle value:0x2a  
 
MMDC0 MPWRDLCTL = 0x2A2A2C26  
 
 
   MMDC registers updated from calibration   
 
   Write leveling calibration  
   MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F0023  
   MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002B001F  
 
   Read DQS Gating calibration  
   MPDGCTRL0 PHY0 (0x021b083c) = 0x4166016D  
   MPDGCTRL1 PHY0 (0x021b0840) = 0x016D016B  
 
   Read calibration  
   MPRDDLCTL PHY0 (0x021b0848) = 0x30282C2C  
 
   Write calibration  
   MPWRDLCTL PHY0 (0x021b0850) = 0x2A2A2C26  
 
 
Success: DDR calibration completed!!!

use the rebuild u-boot .imx ,can boot from mfgtool in windows pc

U-Boot 2015.04-14468-gd7d7c43-dirty (Aug 24 2016 - 09:59:41)

CPU: Freescale i.MX6Q rev1.5 at 792 MHz
CPU: Temperature 42 C
Reset cause: POR
Board: MX6Q-GWI-SCANNER revA
I2C: ready
DRAM: 1 GiB
PMIC: PFUZE100 ID=0x10
MMC: MMC/SD: Reset never completed.
voltage not supported by controller

SF: Unsupported flash IDs: manuf 00, jedec 0000, ext_jedec 0000
*** Warning - spi_flash_probe() failed, using default environment

In: serial
Out: serial
Err: serial
Net: Phy 0 not found
PHY reset timed out
FEC [PRIME]
Boot from USB for mfgtools
Use default environment for mfgtools
Run bootcmd_mfg: run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};
Hit any key to stop autoboot: 0
Bad Linux ARM zImage magic!
=> md 020d8004 1
020d8004: 00003840 @8..
=> md 020d801c 1
020d801c: 30000011 ...0
=>

but I can not boot from sd4 or spinor ,when I insert sd in sd4 , we measuring the signal  of SD4_CLK In the annex

[igorpadykov]

Hi xuhui

one can to program sd card with another option, please refer to

attached Linux Guide sect.4.3.1 Preparing the card.

If it fails please attach jtag and check SRC_SBMR1,2

they should contain correct boot settings.

What reference design is based custom board, is it i.MX6Q Sabre SD

or other board?

Best regards
igor
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[lixuhui112]

you can see my board is reference design imx6q-sabread-AI ,in uboot-imx is mx6qsabreauto,and I use mfgtool boot the board can see  SRC_SBMR1,2 :

=> md 020d8004 1
020d8004: 00003840 @8..
=> md 020d801c 1
020d801c: 30000011 ...0
=>

[igorpadykov]

one can attach the board with any JTAG debugger and dump 0x907400

(ROM uses 0x907000 as starting address), you should see your IVT header

here if the SD access is ok. Example can be found on

https://community.nxp.com/thread/307723 

[lixuhui112]

I use the JTAG debuger and dump 0x907400 , it can read IVT header ,but  usb also jump to the HID (Serial down mode )

[igorpadykov]

then based on destination addresses in ivt header one can check ddr:

uboot should be copied to ddr.