imx6ULL EIM CS invalid

[Levear]

Hello everyone, my question now is that when using DMA to read data from the FIFO of FPGA on the EIM interface, both the CS signal and OE signal are normal. However, when using direct memory reading and writing, the CS signal remains invalid. Here is my code. Does anyone know what the problem is?

#define FPGA_BASE 0x50000000

#define REG_PULSE (*((volatile unsigned short *) (FPGA_BASE + 0x0002)))

BOARD_InitPins();
BOARD_BootClockRUN();
BOARD_InitMemory();
BOARD_InitDebugConsole();
BOARD_InitModuleClock();
SystemInitIrqTable();

while (1)
{

REG_PULSE = temp;

temp = FPGA_BASE;
}

Board_ InitMemory() uses code from the official SDK and has not made any modifications。

[Sanket_Parekh]

Hello @Levear,

I hope you are doing well.

Thanks for sharing the code snippet, I checked it.
In addition to that I have a few queries to ask, Please find them below.

Which Linux BSP are you using?
What NXP EVK are you using?
Please share the dmesg logs as well as the environmental details.

Thanks & Regards,
Sanket Parekh

[Levear]

The previous issue has been resolved, it is due to the FPGA program。There is a new problem, in synchronous mode (Burst len=32), when I write data to addresses 0x50000000 (FPGA corresponding address 0x0000) and 0x50000002 (0x0001) using two variables, as shown in the following figure, the FPGA only grabs an address of 0x0000 and does not have 0x0001. However, when I replace 0x5000002 with 0x50000040, the FPGA can grab an address of 0x0020.

[Levear]

NO_SYS
SDK_2.2_MCIM6ULL_RFP_Win

[ceggers]

Maybe the CPU cannot access the EIM in you current setup. Please check the settings of AIPSTZ and MMU.

[Levear]

thank you !  you  are right  .

The official SDK defaults to setting memory to s_ MmuRamAttr, it should be set to s_ MmuBufferAttr, the specific differences are as follows

This way, the CS and RW signals are normal, but there is another issue: reading data is normal, but when writing data, the data received by the FPGA on the data bus is always 0, which is strange？