Hi,
Our customer E4D raised the following question:
Questions have arisen around whether we can just wire up the differential pairs for:
Clock Lane, Data Lane 0, Data Lane 1, Data Lane 2, Data Lane 3 directly to the i.mx8MPlus's 1st CSI port "CSI1",
or do we need to provide the low-speed signaling out of the FPGA also. That involves still involves only differential pairs
going into the i.mx8, but the FPGA has to provide extra output pins and termination to allow the extra pins to drive low-speed bi-directional
signaling.
What raises the question is that Lattice shows multiple ways to wire up the part, one of which omits the LS (low-speed) signaling.
It would simplify our design, but we are unsure whether it would work, as most sources claim you need both HS and LS signaling support
for MIPI-CSI2 to work.
Can you confirm whether the i.mx8MPlus requires the low-speed signaling? And if not, how to configure the part to allow high-speed only?
For reference, this is the interfacing Lattice proposes for HS & LS signaling:
And this is the interfacing they propose for HS-only signaling:
Thanks.
Ayman
