iMX6: how to trigger software reset

[rafalwegner]

Hello

Does anyone knows and could describe the procedure of how to trigger a reset of the board (power off / power on) from software (u-boot application)?

I believe some of the SRC registers should be configured properly to obtain such behaviour.

Thanks very much in advance

BR, Rafal

[zlhuang]

Thanks, Yongcai.

Do you mean it's the hardware circuit issue?

I will monitor the POR pin and report the result.

[rafalwegner]

Hello

Thanks for your answer but what I actually would like to do is to reset the i.MX6 SOC from standalone program run in u-boot. From within this standalone program I would like to have the same behaviour (reset of iMX6) as user can trigger by running "reset" command in u-boot prompt.

Do you know how to trigger a wdog reset using internal iMX6 registers? Those settings of registers are what I am looking for.

BR, Rafal

[AnsonHuang]

Hi，Rafal

       Sorry for taking your question in wrong way, below are the answers:

        To trigger wdog reset, you can write 0x4 to wdog's control register, it's address should be 0x21bc000, it is a 16 bits register, you need to write it in 16 bits access.

         For SRC register, bit 0 of SRC_SCR register is to control whether you want a warm reset of cold reset of system. It's address should be 0x20d8000.

          Please try it and let me know the result, thanks.

[mrleo]

Dear Yongcai,

Since my board hardware problem, I need to a warm reset my board  with the WDOG1, like uboot "reset", only reset POR.

freescale code default support WDOG2,a cold reset.Third-party kernel like openwrt imx6q kernel support warm reset.

I modify some code below：

1.arch/arm/mach-mx6/cpu.c

/* Disable SRC warm reset to work aound system reboot issue */

  base = IO_ADDRESS(SRC_BASE_ADDR);

  reg = __raw_readl(base);

  //reg &= ~0x1;

  reg |=0x1;//force SRC warm reset  add 20140421

  __raw_writel(reg, base);

2.arch/arm/plat-mxc/system.c

//add

#define SRC_SCR 0x000

#define SRC_GPR1 0x020

#define BP_SRC_SCR_WARM_RESET_ENABLE 0

#define BP_SRC_SCR_CORE1_RST 14

#define BP_SRC_SCR_CORE1_ENABLE 22

void imx_src_prepare_restart(void)

{

  u16 val;

  /* clear enable bits of secondary cores */

  val = __raw_readw(IO_ADDRESS(0x20d8000));//src_scr

  val &= ~(0x7<< BP_SRC_SCR_CORE1_ENABLE);

  printk("SRC_SCR=0x%x\n",val);//val=521

  //__raw_writew(0,IO_ADDRESS(0x20bc008));//WDOG_WMCR diable counter optertion

  /* clear persistent entry register of primary core */

  __raw_writew(0,IO_ADDRESS(0x20d8020));//src_gpr1 core1

  __raw_writew(0,IO_ADDRESS(0x20d8024));

  __raw_writew(0,IO_ADDRESS(0x20d8028));//core2

  __raw_writew(0,IO_ADDRESS(0x20d802c));

  __raw_writew(0,IO_ADDRESS(0x20d8030));

  __raw_writew(0,IO_ADDRESS(0x20d8034));//core3

  __raw_writew(0,IO_ADDRESS(0x20d8038));

  __raw_writew(0,IO_ADDRESS(0x20d803c));//core4

}

void arch_reset(char mode, const char *cmd)

{

  unsigned int wcr_enable;

  printk("%s\n",__FILE__);

  arch_reset_special_mode(mode, cmd);

  imx_src_prepare_restart();

#ifdef CONFIG_ARCH_MX6

#if 0

  /* wait for reset to assert... */

  if (enable_ldo_mode == LDO_MODE_BYPASSED) {

  /*On Sabresd board use WDOG2 to reset external PMIC, so here do

  * more WDOG2 reset.*/

  printk("WDOG2\n");

  wcr_enable = 0x14;

  __raw_writew(wcr_enable, IO_ADDRESS(MX6Q_WDOG2_BASE_ADDR));

  __raw_writew(wcr_enable, IO_ADDRESS(MX6Q_WDOG2_BASE_ADDR));

  } else

#endif

  wcr_enable = 0x4;

  __raw_writew(wcr_enable, wdog_base);

  /* errata TKT039676, SRS bit may be missed when

  SRC sample it, need to write the wdog controller

  twice to avoid it */

  __raw_writew(wcr_enable, wdog_base);

  /* wait for reset to assert... */

  mdelay(500);

  printk(KERN_ERR "Watchdog reset failed to assert reset\n");

  mdelay(500);

  return;

#endif

}

But also not reboot the system？ imx6q linux 3.0.35 can support software warm reset or not?

If can,what should I do?

[AnsonHuang]

We do NOT support warm reset in our BSP, if you want to use warm reset, LDO bypass will be not supported, and MMDC auto self-refresh must be disabled.

May I know why you want to use WARM reset? COLD reset is OK for you, I thought you just NOT want the WDOG to trigger external PMIC reset, then code reset should be OK for you, right?

[mrleo]

Dear Yongcai,

I am very sorry ,Because of my board hardware problem,cold reset in not ok for me , I need to a warm reset my board  with the WDOG1,like in uboot reset.

if i want to use warm reset, how to disable LDO bypass , and MMDC auto self-refresh.

Thanks

Leo

[AnsonHuang]

uboot reset can also be colde reset, we have three kinds of reset, you can refer to RM for detail, I think cold reset is OK for you, you just don't want a power reset, right? To disable LDO bypass, for L3.0.35, you can add "ldo_active=on" to kernel command line, after kernel boot up, you can measure the VDDARM_IN, it should be 1.375V for 1GHz part. Then no need to disable MMDC auto self-refresh if using cold reset.

[mrleo]

Thanks very much！It is ok for me！

[AnsonHuang]

Great, I am glad to hear that:)

[rafalwegner]

Hi

Thanks very much for your input. I am working on iMX6 DualLite processor and to trigger wdog reset I had to clear fourth bit of WDOG1_WCR register (0x020bc000). Now my program works as I needed.

Best Regards

Rafal