i.mx6ul booting problem

Gopiaffluence · ‎02-16-2021

Dear All

We designed a custom board with i.mx6UL processor. While booting the processor is getting struck at the below point. Can any one suggest what can be the problem.

U-Boot 2015.04-dirty (Feb 15 2021 - 15:17:44)

CPU: Freescale i.MX6UL rev1.2 at 396 MHz

CPU: Temperature 37 C

Reset cause: POR

Board: MX6UL 14x14 EVK

I2C: ready

DRAM: 512 MiB

force_idle_bus: sda=0 scl=0 sda.gp=0x1d scl.gp=0x1c

MMC: FSL_SDHC: 0, FSL_SDHC: 1

*** Warning - bad CRC, using default environment

Display: TFT43AB (480x272)

Video: 480x272x24

In: serial

Out: serial

Err: serial

switch to partitions #0, OK

mmc0 is current device

Net: FEC1

Error: FEC1 address not set.

Normal Boot

Hit any key to stop autoboot: 0

switch to partitions #0, OK

mmc0 is current device

switch to partitions #0, OK

mmc0 is current device

reading boot.scr

** Unable to read file boot.scr **

reading zImage

5479728 bytes read in 480 ms (10.9 MiB/s)

Booting from mmc ...

reading imx6ul-14x14-evk.dtb

37316 bytes read in 22 ms (1.6 MiB/s)

Kernel image @ 0x80800000 [ 0x000000 - 0x539d30 ]

## Flattened Device Tree blob at 83000000

Booting using the fdt blob at 0x83000000

Using Device Tree in place at 83000000, end 8300c1c3

Modify /soc/aips-bus@02000000/bee@02044000:status disabled

ft_system_setup for mx6

Starting kernel ...

Uncompressing Linux... done, booting the kernel.

Can any one suggest where can be the problem and where to look.

igorpadykov · ‎02-23-2021

if ddr test passed, update dcd header with calibration settings from ddr test. Then

one can try to decrease CMA as suggested in sect.11 DDR size and Contiguous Memory Allocator

https://variwiki.com/index.php?title=VAR-SOM-MX6_Yocto_Dizzy_R1

Best regards
igor

View solution in original post

igorpadykov · ‎02-16-2021

Hi Gopiaffluence

this may be caused by ddr errors, one can run ddr test

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-6-7-DDR-Stress-Test-Tool/ta-p/11082...

and update uboot dcd header with new ddr calibration settings found from ddr test

https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/mx6ul_14x14_evk/imximage.c...

Best regards
igor

Gopiaffluence · ‎02-17-2021

Dear Igor,

Thank you for your prompt reply.

We are using the I.MX6UL evaluation board kernel. The differences between I.MX6UL evaluation board and our custom board are as follows.

1. eSDHC-1 has been connected to SD card and eSDHC-2 is been connected to eMMC.

2. The DDR3L RAM size used in custom board is 1Gb(128MB, MT41K64M16TW ) and in evaluation board it is (4Gb, MT41K256M16TW).

3. Only USB_OTG1 is connected and left USB_OTG2 open.

4. We left CSI interface open.

5. The ENET port is. been used for GPIO and NOR FLASH.

We tried to test the DDR as suggested by using U-BOOT option. We are not able to locate "ddr-test-uboot-jtag-mx6ul.bin." The below is the log file.

CPU: Freescale i.MX6UL rev1.2 at 396 MHz

CPU: Temperature 42 C

Reset cause: POR

Board: MX6UL 14x14 EVK

I2C: ready

DRAM: 512 MiB

force_idle_bus: sda=0 scl=0 sda.gp=0x1d scl.gp=0x1c

MMC: FSL_SDHC: 0, FSL_SDHC: 1

*** Warning - bad CRC, using default environment

Display: TFT43AB (480x272)

Video: 480x272x24

In: serial

Out: serial

Err: serial

switch to partitions #0, OK

mmc0 is current device

Net: FEC1

Error: FEC1 address not set.

Normal Boot

Hit any key to stop autoboot: 0

=> dcache off

=> icache off

=> fatload mmc 0:1 0x00907000 ddr_stress_tester_uboot_v3.00_setup.exe

reading ddr_stress_tester_uboot_v3.00_setup.exe

565248 bytes read in 83 ms (6.5 MiB/s)

=> go 0x00907000

## Starting application at 0x00907000 ...

undefined instruction

pc : [<00907004>] lr : [<9ff57c80>]

reloc pc : [<e81b5004>] lr : [<87805c80>]

sp : 9ef4fd50 ip : 9ff86b08 fp : 00000000

r10: 00000002 r9 : 9ef4feb8 r8 : 9ffa2490

r7 : 9ef507b0 r6 : 00907000 r5 : 00000002 r4 : 9ef507b4

r3 : 00907000 r2 : 9ef507b4 r1 : 9ef507b4 r0 : 00000001

Flags: nZCv IRQs off FIQs off Mode SVC_32

Resetting CPU ...

resetting ...

igorpadykov · ‎02-17-2021

Hi Gopiaffluence

please try to run ddr test using usb

https://community.nxp.com/t5/NXP-FTF-2016-Training/DES-N1936-i-MX-6UltraLite-DDR-Tools-Overview-and-...

Best regards
igor

Gopiaffluence · ‎02-17-2021

We are testing the RAM with MTEST command will it be sufficient? we are still facing problem with the USB access.. While testing with MTEST the device is passing the test when we performed the test multiple times.

igorpadykov · ‎02-17-2021

not, it is not suficient. First please bring-up usb using

Hardware Development Guide for the i.MX 6UltraLite Applications Processor

Best regards
igor

Gopiaffluence · ‎02-18-2021

Hi Igor,

We performed the stress test on DDR3 and the unit is passing the test. Still the unit is getting struck at loading kernel as described below.

Please find the DDR stress test report below.

U-Boot 2015.04-dirty (Feb 15 2021 - 15:17:44)

CPU: Freescale i.MX6UL rev1.2 at 396 MHz
CPU: Temperature 54 C
Reset cause: POR
Board: MX6UL 14x14 EVK
I2C: ready
DRAM: 512 MiB
force_idle_bus: sda=0 scl=0 sda.gp=0x1d scl.gp=0x1c
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environment

Display: TFT43AB (480x272)
Video: 480x272x24
In: serial
Out: serial
Err: serial
switch to partitions #0, OK
mmc0 is current device
Net: FEC1
Error: FEC1 address not set.

Normal Boot
Hit any key to stop autoboot: 0
=> dcache off
=> icache off
=> fatload mmc 0:1 0x00907000 ddr-test-uboot-jtag-mx6ul.bin
reading ddr-test-uboot-jtag-mx6ul.bin
66852 bytes read in 33 ms (1.9 MiB/s)
=> go 0x00907000
## Starting application at 0x00907000 ...

============================================
DDR Stress Test (3.0.0)
Build: Dec 14 2018, 14:21:04
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 UltraLite(0x64)
Internal Revision = TO1.2
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000000
SRC_SBMR2(0x020d801c) = 0x00000041
============================================

What ARM core speed would you like to run?
Type 1 for 200MHz, 2 for 400MHz, 3 for 528MHz, 4 for 700MHz
ARM Clock set to 400MHz

============================================
DDR configuration
DDR type is DDR3
Data width: 16, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 512MB
============================================

Current Temperature: 58
============================================

Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB
DDR density selected (MB): 128

Would do you want to change VDD_SOC_CAP/VDD_ARM_CAP voltage? Type 'y' to run and 'n' to skip

Would do you want run DDR Calibration? Type 'y' to run and 'n' to skip

The DDR stress test can run with an incrementing frequency or at a static freq
To run at a static freq, simply set the start freq and end freq to the same value
Would do you want run DDR Stress Test? Type 'y' to run and 'n' to skip

Enter desired START freq (135 to 672 MHz), then hit enter.
Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.
400
The freq you entered was: 400

Enter desired END freq (135 to 672 MHz), then hit enter.
Make sure this is equal to or greater than start freq
400
The freq you entered was: 400

Do you want to run DDR Stress Test for simple loop or Over Night Test?
Type '0' for simple loop. Type '1' for Over Night Test

DDR Stress Test Iteration 1
Current Temperature: 57
============================================

DDR Freq: 396 MHz
t0.1: data is addr test
t0: memcpy11 SSN test
t1: memcpy8 SSN test
t2: byte-wise SSN test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

DDR Stress Test is complete!

Could you please suggest us how to proceed further.

igorpadykov · ‎02-18-2021

next step is to update uboot dcd header with new ddr calibration settings found from ddr test

and rebuild uboot:

https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/mx6ul_14x14_evk/imximage.c...

This is described in sect.3.2.1 Changing the DCD table for i.MX DDR initialization

Porting Guide included in L4.1.15 Documentation

Also may be useful to check p.8 "PHYS_SDRAM_SIZE".

Best regards
igor

Gopiaffluence · ‎02-23-2021

Hi Igor,

As suggested we performed the DDR calibration. Could you please let us know whether it is correct or not and how to proceed further?

igorpadykov · ‎02-23-2021

if ddr test passed, update dcd header with calibration settings from ddr test. Then

one can try to decrease CMA as suggested in sect.11 DDR size and Contiguous Memory Allocator

https://variwiki.com/index.php?title=VAR-SOM-MX6_Yocto_Dizzy_R1

Best regards
igor

Gopiaffluence · ‎02-23-2021

Hi Igor,

We are able to load the kernel now. Main change we have done is changing the DDR size to 128MB.

Thanks you for the help and guidance. We will work on proving other interfaces and come back to you if we need any help.

Thanks you so much for the guidance and help.

Gopiaffluence · ‎02-18-2021

We updated the DDR calibration settings as below after performing the calibration.. We are still facing the same problem. The DDR settings updated are

Write leveling calibration
   MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00060000   Read DQS Gating calibration
   MPDGCTRL0 PHY0 (0x021b083c) = 0x41580158
   MPDGCTRL1 PHY0 (0x021b0840) = 0x00000000   Read calibration
   MPRDDLCTL PHY0 (0x021b0848) = 0x40405250   Write calibration
   MPWRDLCTL PHY0 (0x021b0850) = 0x4040524C

Could you please let us know hoe to proceed further.