i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working

[malkai]

Hello,

I am trying to debug firmware for the Cortex-M33 on an i.MX93 using a Segger J-Link and gdb. I established an SWD connection using the patch from NXP for the J-Link software and can halt the processor, read the registers and memory and so on.
My problem is, that resetting the processor does not work. The content of the registers does not change so I assume the reset is ignored:

(gdb) monitor regs
R0 = 40D000C0, R1 = 2001EFE3, R2 = 40D000C0, R3 = 00000000
R4 = 00000000, R5 = 00000000, R6 = FFFFFFFF, R7 = 2001EEE8
R8 = FFFFFFFF, R9 = FFFFFFFF, R10= 2000F000, R11= 00000000
R12= FFFFFFFF, R13= 2001EEE8, MSP= 2001EEE8, PSP= 00000000
R14(LR) = 0FFE219D, R15(PC) = 0FFE2248
XPSR 49000003, APSR 48000000, EPSR 01000000, IPSR 00000003
CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00

Security extension regs:
MSP_S = 2001EEE8, MSPLIM_S = 00000000
PSP_S = 00000000, PSPLIM_S = 00000000
MSP_NS = 00000000, MSPLIM_NS = 00000000
PSP_NS = FFFFFFFC, PSPLIM_NS = 00000000
CONTROL_S 00, FAULTMASK_S 00, BASEPRI_S 00, PRIMASK_S 00
CONTROL_NS 00, FAULTMASK_NS 00, BASEPRI_NS 00, PRIMASK_NS 00

(gdb) monitor reset
Resetting target
(gdb) monitor regs
R0 = 40D000C0, R1 = 2001EFE3, R2 = 40D000C0, R3 = 00000000
R4 = 00000000, R5 = 00000000, R6 = FFFFFFFF, R7 = 2001EEE8
R8 = FFFFFFFF, R9 = FFFFFFFF, R10= 2000F000, R11= 00000000
R12= FFFFFFFF, R13= 2001EEE8, MSP= 2001EEE8, PSP= 00000000
R14(LR) = 0FFE219D, R15(PC) = 0FFE2248
XPSR 49000003, APSR 48000000, EPSR 01000000, IPSR 00000003
CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00

Security extension regs:
MSP_S = 2001EEE8, MSPLIM_S = 00000000
PSP_S = 00000000, PSPLIM_S = 00000000
MSP_NS = 00000000, MSPLIM_NS = 00000000
PSP_NS = FFFFFFFC, PSPLIM_NS = 00000000
CONTROL_S 00, FAULTMASK_S 00, BASEPRI_S 00, PRIMASK_S 00
CONTROL_NS 00, FAULTMASK_NS 00, BASEPRI_NS 00, PRIMASK_NS 00

The reset strategy from the J-Link is using SYSRESETREQ and not the reset signal since only the Cortex-M33 core is supposed to be reset. Is it possible that the debug controller does not have the necessary security privileges to write the SYSRESETREQ bit?

What is the correct way to perform a reset of the Cortex-M33 using a J-Link?

Regards,
Malte

[kabart]

Hi, I just found this topic and was wondering if someone was finally able to find some reliable solution for working with M33 in separation from A55. Recently I have started creating development environment for upcoming project and pretty quickly got into the same trouble with triggering software reset. It's been some time since the thread was opened, SEGGER now (v8.10) provides software with builtin IMX targets, although still seems not capable of performing single core reset. I did some experiments with SCB (SYSRESETREQ) and SCR registers but just can't achieve anything stable. I had also quickly tested MCUXpresso plugin for VSCode and didn't notice any custom, working reset strategy implementation.

Regards,

Krzysztof

[malkai]

Hello Krzysztof,

as stated above, I did manage to work out a way to reset the Cortex-M33 in an i.MX93 using a J-Link. If that is what you are looking for, I will gladly share the details with you. Just tell me your e-mail address or another way of contacting you directly.

Regards,
Malte

[Z2025121]

Hi Malkai, I am very much interested in a solution as I get exactly the same problem. Is it possible to send me your solution or advice? Many thanks. j.zhang3@krohne.com

Best regards

Junshu

[malkai]

Hello @Sanket_Parekh,

thank you for your reply. Unfortunately, that information is not helping to solve my problem. In the meantime, I found out multiple things:

1. The J-Link script provided by NXP in the patch for the i.MX93 does not implement a reset. It replaces resetting the CPU with just halting it.
2. Requesting a reset by manually writing AICR.SYSRESETREQ to 1 through the debugger does not result in a reset of the Cortex-M33 core.

So, my original question remains: What possibility exits to reset the Cortex-M33 through a debugger?

Thanks and regards,
Malte

[Sanket_Parekh]

Hello @malkai ,

I hope you are doing well.

->The Reset selection controls the target device reset operation. All reset options apply to Cortex-M processor-based devices, are available in JTAG and SWD mode, and halt the CPU after the reset.

->Core - performs a reset of the Cortex-M core only by setting the VECTRESET bit. On—chip peripherals are not reset. For some Cortex—M devices, this reset method is the only way they may be reset. However, in most cases, this method is not recommended, because most target applications rely on the reset state of some peripherals (PLL, External memory interface, etc.) and may be confused if they boot up, but the peripherals are already configured.

->ResetPin - J-Link pulls its RESET pin low to reset the core and peripherals. Normally, this causes the CPU RESET pin of the device to go low as well, resulting in a reset of the CPU and peripherals. This reset method will fail if the RESET pin of the target device is not pulled low.

Please refer to the section reset strategies in the below link.
https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/kinetis/28743/1/UM08001_JLink.pdf

Thanks & Regards,
Sanket Parekh

[Z2025121]

Hello Sanket_Parekh,

(1) Where can I get the NXP J-Link script patch for i.MX93 Cortex-M33?

(2) According to Segger there is no roadmap yet to support i.MX93 in J-Link. But it make come in Q1/Q2. Is there any other possibilities to debug the Cortex-M33?

BR

[malkai]

Hello @Sanket_Parekhm,

thank you for your reply. However, that information does not help to solve the issue. As you know, the Cortex-M33 core in the i.MX93 has the Armv8-M architecture which does not have a VECTRESET bit in the AIRCR register (see D1.2.3 in https://developer.arm.com/documentation/ddi0553/latest/). So the only available reset request is SYSRESETREQ to which there is no reaction by the Cortex-M33 core nor by the entire system. Why is that?

I already looked into the reset strategies used by the J-Link. The thing is, that the patch from NXP replaces these with just halting the CPU, as I told you. And the reset line cannot be used here, since it resets the entire SoC.

So, the issue still remains: What is the procedure intended by NXP to reset the Cortex-M33 core in the i.MX93?

Thank you and kind regards,
Malte Kaiser

[Sanket_Parekh]

Hello @malkai ,

I hope you are doing well.

"What is the procedure intended by NXP to reset the Cortex-M33 core in the i.MX93?"
->The System Reset Controller (SRC) is responsible for the generation of all the system reset signals and boot argument latching.

->Its main functions are as follows:
• Deals with all global system reset sources from other modules and generates global system reset.
• Responsible for power gating of MIXs (Slices) and their memory low power control.

->The SRC takes the POR_B from the PAD and fuse bits to complete the boot sequence and the GPC low power request to
complete the power down/up sequence.

Please refer to Chapter 33 System Reset Controller (SRC).
https://www.nxp.com/webapp/Download?colCode=IMX93RM

Thanks & Regards,
Sanket Parekh

[NielsGM]

Hello @Sanket_Parekh 

I'm in the exact same situation as the original author. It appears that the JLink script provided by NXP doesn't actually reset the M33 core, but only halts it. This leaves registers and processor state unchanged and if a fault was encountered, I'm not able to continue debugging properly without resetting the core through Linux first.

Is there any way that I can trigger such a reset of the M33 core but using the JLink debugger?

Best regards

Niels

[malkai]

Hi Niels,

no thanks to the NXP support, which is less than helpful, I worked out a solution for this problem.
If you tell me your e-mail address or any other way of contacting you directly I will be glad to help you.

Kind regards,
Malte Kaiser

[NielsGM]

Hi Malte

That would be much appreciated. My mail is nim@develcoproducts.com

Best regards

Niels

[Sanket_Parekh]

Hello @malkai,

I hope you are doing well.

Please refer to this link, It will be helpful.
https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/All-Boards-JTAG/ta-p/1106822

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Thanks & Regards,
Sanket Parekh