Hi,
We are looking to implement a system with an external DAC and ADC. The external DAC and ADC are expected to run at a speed of around 100MHz with a resolution of 12 bits. We have spotted the i.MX 8 and think it could do the job for that. Here is the peripheral we thought we could use.
First a GPT could generate a clock at 100 MHz (in the documentation, it says that 100MHz is it's maximum seed).
A DMA transfer would be triggered by the GPT. The DMA transfer would write or read a 16 bit value from the DAC/ADC.
The ADC/DAC would be connected to the microcontroller via the DDRC peripheral. This is the part where we are not sure. Since the DAC and ADC have a parallel interface, we guess this would be possible if we mapped an address to the DAC and another to the ADC. The DMA could send data to the ADC or read the data from the DAC via a read or write command to the DDRC peripheral.
Is this a viable use of the peripheral? We were wondering if the use of an external clock that, via a pin would trigger the DMA, would be a better idea since the GPT is at his speed limit. We are also wondering if the DDRC peripheral can be used has a DAC/ADC interface. Maybe the GPIO could do the job at this speed... We have not found the maximum speed of the GPIO and IOMUX peripheral.
Thank you for your time,
Leo
