We're working on a custom board based on the i.MX7D and have LPSR mode working mostly, but we have not been able to resume from GPIO. Currently from LPSR, we can resume from RTC and ONOFF button only. In suspend-to-memory, we are able to resume from RTC, ONOFF, as well as GPIOs without any issue.
For reference, NVCC_GPIO1/2 are valid during LPSR, VDD_LPSR and VDD_SNVS are also valid as well as the memory rails needed for self refresh. We do observe the GPIO toggling when probing it externally so it seems to be a configuration issue.
In STM, we can wake from gpio using all the regular methods including: using device tree with gpio-keys using the wakeup flag, from system using /sys/class/gpio, as well as by requesting gpio/irq from another driver. However, none of these methods allow for LPSR based wakeup.
Since in LPSR mode the A7s are in an ALL_OFF state, I'm thinking it may be an issue with the GPCv2 configuration masking the GPIO wakeups.
I'm curious if someone could shed some light on this or could refer to an example code base where LPSR GPIO resume is functioning (such as on the arm2 board).
Thank you,
Hello,
The minimum power domains needs to be on for LPSR are VDD_SNVS, VDD_LPSR and NVCC_DRAM, then it supports RTC alarm wakeup and ON/OFF button wakeup, as these two wakeup sources are inside SNVS domain. If users need GPIO wakeup, then the dedicated GPIO bank power should be on, such as NVCC_GPIO1/NVCC_GPIO2, one for 1.8V and the other for 3.3V.
How to submit a new question for NXP Support
Have a great day,
Yuri
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Hi Aaron,
Would it be fair to ask whether you ever were able to resolve this issue? We are are also doing a custom i.MX7D design with DDR3L memory and have LPSR working but it does not exit LPSR on an interrupt transition from our Pcap touch panel (specifically GPIO1_IO07 input). It appears that Yuri was encouraging you to create a support request, so I'm wondering if you were able to get any resolution through that channel?
Thanks,
Bill
Hi Bill,
We did eventually resolve this and are able to wake from LPSR from GPIO by setting bit 7 in register 0x30370048.
I imagine this should be done in the gpio or interrupt controller, but may not be hooked up correctly for LPSR on the mx7 yet?
As a quick test, you can run this from uboot command line before booting:
mw 0x30370048 0x80 1
Or from code:
writel(0x80, 0x30370048);
Then proceed with your preferred configuration for waking from gpio from driver, fs or dts such as:
Feel free to shoot me a PM if that doesn't work.