i.MX7D DDR3 calibration and Script Aid

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i.MX7D DDR3 calibration and Script Aid

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rasmusrahunen
Senior Contributor I

Hi all,

We are building a product, which is based on i.MX7D SABRE board. We would need to calibrate the DDR3 memories with our prototype device. We have downloaded the i.MX6/7 DDR Stress Test Tool from:

 i.MX6/7 DDR Stress Test Tool V2.60 

I have a couple of questions:

1. Is there a similar DDR3 script aid available for i.MX7D that exists for i.MX6? (i.MX6DQSDL DDR3 Script Aid )

2. Is the script provided with the tool "MX7D_DDR3_register_programming_aid_v09.ds" actually valid for the SABRE development board? - If so, then it's probably also valid for us, since the memory design is based on SABRE.

I've tried running the calibration with the above mentioned default script and it yields the following results with 528MHz DDR frequency:


Final read delay = 0x0C0C0C0C

Final write delay = 0x06060606

The final question is:

3. After the calibration, is it enough to enter these two values into the U-Boot configuration file (like here: git.denx.de Git - u-boot.git/blob - board/freescale/mx7dsabresd/imximage.cfg ) registers DDR_PHY_OFFSET_RD_CON0 (0x30790020) & DDR_PHY_OFFSET_WR_CON0 (0x30790030)?

Best regards,

Rasmus

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jamesbone
NXP TechSupport
NXP TechSupport

Hello Rasmus,

1. Is there a similar DDR3 script aid available for i.MX7D that exists for i.MX6?

ANSWER. Yes, we have but it is only for Internal Use Only, since it is under development. If you want more details please enter a CASE, so we can discuss it in private.

Is the script provided with the tool "MX7D_DDR3_register_programming_aid_v09.ds" actually valid for the SABRE development board? - If so, then it's probably also valid for us, since the memory design is based on SABRE.

ANSWER. Yes, it is valid.

3. After the calibration, is it enough to enter these two values into the U-Boot configuration file (like here: git.denx.de Git - u-boot.git/blob - board/freescale/mx7dsabresd/imximage.cfg ) registers DDR_PHY_OFFSET_RD_CON0 (0x30790020) & DDR_PHY_OFFSET_WR_CON0 (0x30790030)?

ANSWER.The DRAM controller IP in MX7D is different from the MX6 series MMDC controller. Results from DRAM calibration may be updated for the following registers: DDR_PHY_OFFSET_WR_CON0 (0x30790030) and DDR_PHY_OFFSET_RD_CON0 (0x30790020).  Also, the MX7D memory map DRAM starting address is fixed at 0x80000000.


Have a great day,
Jaime

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jamesbone
NXP TechSupport
NXP TechSupport

Hello Rasmus,

1. Is there a similar DDR3 script aid available for i.MX7D that exists for i.MX6?

ANSWER. Yes, we have but it is only for Internal Use Only, since it is under development. If you want more details please enter a CASE, so we can discuss it in private.

Is the script provided with the tool "MX7D_DDR3_register_programming_aid_v09.ds" actually valid for the SABRE development board? - If so, then it's probably also valid for us, since the memory design is based on SABRE.

ANSWER. Yes, it is valid.

3. After the calibration, is it enough to enter these two values into the U-Boot configuration file (like here: git.denx.de Git - u-boot.git/blob - board/freescale/mx7dsabresd/imximage.cfg ) registers DDR_PHY_OFFSET_RD_CON0 (0x30790020) & DDR_PHY_OFFSET_WR_CON0 (0x30790030)?

ANSWER.The DRAM controller IP in MX7D is different from the MX6 series MMDC controller. Results from DRAM calibration may be updated for the following registers: DDR_PHY_OFFSET_WR_CON0 (0x30790030) and DDR_PHY_OFFSET_RD_CON0 (0x30790020).  Also, the MX7D memory map DRAM starting address is fixed at 0x80000000.


Have a great day,
Jaime

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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rasmusrahunen
Senior Contributor I

Hi Jaime,

Thank you, this is clear now. We will enter a CASE about the script aid.

Best regards,

Rasmus

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