i.MX6UltraLite 9X9 Pinout

[ricardoferreira]

Hi,

In the datasheet of the i.MX6Ultralite, the pinout description has for the pin N6 NVCC_DRAM_2P5 and for th pin K6 VSS.

On the reference design for the evualation board of this processor, K6 is NVCC_DRAM_2P5 AND N6 is NVCC_DRAM4 (picture in attach).

Could someone tell me what should be the correct pinout?

Thanks a lot.

Regards,

Ricardo F.

[art]

Oh, sorry, Ricardo.

The ballmap Table 96 of the i.MX6UL Data Sheet shows NVCC_DRAM_2P5 as K6 for the 9x9 package, and this is correct. The confusing point is that the Table 94 contains a typo showing NVCC_DRAM_2P5 as N6, and this is wrong.

So, finally, the answer is: NVCC_DRAM_2P5 is located on the ball K6 on the 9x9mm i.MX6UL package.

Once again, sorry for confusing you.

Best Regards,

Artur

[art]

The i.MX6UL EVK board uses 14x14mm part, for which K6 as NVCC_DRAM_2P5 and N6 as NVCC_DRAM4 is the correct pinout. For 9x9xmm part, the correct pinout is N6 as NVCC_DRAM_2P5 and K6 as VSS. In both cases, the Data Sheet document is correct.

Have a great day,
Artur

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[ricardoferreira]

Hi,

Actually in the design of the i.MX6UL EVK 14x14mm the datasheet says NVCC_DRAM_2P5  is N6 not K6.

So I got one answer of Igor saying for the 9x9mm the correct ball for the NVCC_DRAM_2P5 is K6 and an answer from Artur saying that the pin is N6.

Could some of you just confirm me this again. We are about to send our board to production and this was spotted just now.

Thanks a lot

[igorpadykov]

Hi Ricardo

the correct ball number for NVCC_DRAM_2P5 is K6, as

confirmed by application team.

Best regards

igor

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Note: If this post answers your question, please click the Correct Answer button. Thank you!

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