i.MX6Q boot ROM occasionally fails

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i.MX6Q boot ROM occasionally fails

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scottkanowitz
Contributor II

I'm having an issue where the boot ROM of an i.MX6Q processor sometimes fails to boot from the selected device. The processor's BOOT_CFG settings are configured via GPIOs and the boot mode pins are set to 1,0 (internal boot). Using the GPIOs I am able to switch the selected boot device between NAND and SD card. The problem happens with both devices.

When the device boots correctly I'm able to see the clock start on the SD card about 16 ms after the processor's reset line is released. When in NAND boot mode I see the same thing on the NAND's CS signal. U-boot is properly loaded from the selected device and the unit runs normally. When the failed boot happens I never see the SD card's clock start or the NAND's CS line get activated.

This problem happens from any kind of reset. I can power on the device, toggle the reset line of the processor, or run the reset command via u-boot. The problem will show up about 20% of the time from any reset condition.

In both cases I'm able to connect to the processor via JTAG. The set of SRC registers (0x020D8000 - 0x020D8044) are the same in both cases. Additionally, the SRC_SBMR1 and SRC_SBMR2 registers match the settings I have configured on the BOOT_CFG GPIO pins.

The registers are:
SRC_SCR = 0x00000521
SRC_SBMR1 = 0x00002040 (SD card boot)
SRC_SRSR = 0x00000001
SRC_SISR = 0
SRC_SIMR = 0x0000001F
SRC_SBMR2 = 0x22000001
SRC_GPR1 - SRC_GPR10 = 0

When I halt the processor via JTAG in the failed case I see the boot ROM running at address 0x00000FC4 and stuck in a loop.

What else can I look at to determine why the boot ROM fails to even access the external memory devices? Are there any memory address the boot ROM uses for status or debug information?

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scottkanowitz
Contributor II

Hi Igor,

Thanks for the reply and info. I've considered a bad solder joint, but the issue doesn't seem to be affected by heat or cold conditions. Also, once the board boots it runs perfectly. It's just the initial boot ROM step that's problematic.

As for the DDR configuration suggestion, I don't think that applies here. The issue happens even before the image is loaded from the NAND or SD card. The DDR isn't relevant at this point in the boot. I could understand if I saw activity on the SD card clock line or NAND CS line and had a failure, but the boot ROM doesn't even get that far.

I reviewed the erratas you sent, but consider that I can reset the processor alone without resetting or power cycling anything else on the board and get the problem to happen.

Is there anything that the boot ROM logs that would help me figure out why it doesn't proceed with the normal boot process? As I mentioned, I'm able to connect to the processor when the boot ROM fails to boot from the selected device. I'm just not sure of what else to look at beyond the SRC registers.

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igorpadykov
NXP Employee
NXP Employee

Hi scottkanowitz

>Is there anything that the boot ROM logs that would help me figure out why it doesn't

>proceed with the normal boot process?

not sorry, there is no easy way to check some ROM boot logs.

Also one can check with logic analyser if there is some activity on emmc/sd/nand.

Other option - change processor from bad board to good, check if issue is related to chip.

General steps for such kind of issues can be found on

https://community.nxp.com/thread/338433 

Best regards
igor

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igorpadykov
NXP Employee
NXP Employee

Hi scottkanowitz

- one can check power up sequence defined in datasheet

i.MX 6Dual/6Quad Applications Processors for Consumer Products - Data Sheet

- try to prolong POR up to 1 sec.

- ERR007926, ERR009678 in

Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus - IMX6DQCE

- also if it is 20% probability issue may be caused by poor soldering, one can try to resolder chip.

- sometimes issue can be resolved after correcting the sequence and the calibration values in the DDR configuration DCD file. May be recommended to run ddr test for problematic boards and update its

dcd header with new calibration coefficients.

https://community.nxp.com/docs/DOC-105652 

Best regards
igor
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