i.MX6Q PCIe : cannot read from 0x0100_0000~0x01FF_BFFF

[masamiyasui]

In i.MX6 Quad, could you tell me the conditions that make the following areas accessible?

  0x0100_0000~0x01FF_BFFF  16,368KB  PCIe

Currently, read access to this area causes an abnormal state (freeze).
(Non-Linux system)

I understand that this area is used for outbound transfer and MSI interrupt.

The register area below can be read and written normally.

  0x01FF_C000~0x01FF_FFFF  16KB  PCIe registers

The current setting is described below.

- PageTable of the corresponding area is defined collectively with other peripherals as a device.

    // 0x01000000 - 0x02bfffff : I/O Access #2

- The PCIe peripheral clock is set as follows.

    CCM_ANALOG_PLL_ENET
      ENABEL=1
      ENABLE_100M=1
      ENABLE_125M=1

      * These are set after confirming that LOCK == 1 after setting POWERDOWN = 0.

    CCM_CCGR4
      CG0=0b11

    IOMUXC_GPR1
      REF_SSP_EN=1

Please let me know if there are other necessary information.

i.mx6q pcie‌#pci express‌#imx6‌

[masamiyasui]

Problem solved.
Thank you for your cooperation.

Under the following conditions, the read access of the corresponding area succeed.

-  Set i.MX 6 to EndPoint Device

-  Link up

-  Set 0x01000000 to the local address of the outbound region (PCIE_PL_iATURLBA)

-  Set the PCIe address published by Root Complex to the target address  of the outbound region (PCIE_PL_iATURLTA)

[masamiyasui]

Sorry for lack of explanation.
The problem I am facing is that it is not a readout via PCI express, it can not be read out merely directly.
For example, freeze with the following code.

val = *((uint32_t *)(0x01000000));     /* this is bare metal system */

[igorpadykov]

for bare-metal please check SDK examples on

Github SDK
https://github.com/backenklee/swp-report/tree/master/iMX6_Platform_SDK

Best regards
igor

[igorpadykov]

is it working in linux ?

http://git.freescale.com/git/cgit.cgi/imx/linux-imx.git/tree/?h=imx_4.9.11_1.0.0_ga 

[igorpadykov]

Hi Masami

please check some restrictions described on

PCIe BAR length limit 

Best regards
igor
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