i.MX6Q: NVCC_RGMII vs NVCC_ENET (or, RGMII vs RMII)

[ilariogottardel]

Good morning to all,

I need to clarify a bit the power rails associated with the network section of i.MX6 quad.

We are developing a SoM that will be used on various products. Devices well be mounted on the base boards, so we need to export all the functions on the connector. Now, what we are trying to achieve with the LAN section is to have a design flexible enough to allow RMII PHY or RGMII PHY based on needs.

Basic assumptions are:

GPIO16 is already used for other things so it's not considered here

Clock is sourced from the PHY, because we already have daughter boards that only provide it

GPIO of our boards are all 3V3, so we really need to remain compatible, the only exception could be the gigabit PHY

Now, if I get it right from Reference Manual, RMII signals are under NVCC_ENET power domain, and RGMII signals are under NVCC_RGMII power domain. But, two of them are inverted: RGMII_TX_CTL pad (C23), which is used by RMII to source the clock, is under NVCC_RGMII power domain, and ENET_REF_CLK pad (V22), which is used by RGMII to source the clock, is under NVCC_ENET.

First question: did I get it right? Are they really inverted like this?

Second question: Why did you make it like this? It doesn't make sense to me.

Third Question: Does this mean that, if we want to make them interchangeable, we must connect the two power rails toghether or use level shifter on the base board? Are there any solutions that well permit us to maintain 3V3 for RMII?

Thank you very much

Have a nice day

[gusarambula]

Hello Ilario Gottardello,

I’m afraid you are correct on the switched domains. Both modes are ultimately tied to the same controller so perhaps it’s a design limitation that level cannot be fully independent. I’m investigating and I’ll let you know if I find more information on why this is.

My recommendation would be using the same voltage level or using the level shifter depending on your desired operation.

My apologies for the inconvenience.

 Regards,

[gusarambula · Accepted solution]

Hello Ilario Gottardello,

I received confirmation. ENET_REF_CLK pad can be used as ENET_TX_CLK output for MII or 125MHz reference clock input for RGMII. For RMII, the 50MHz reference shall be input from GPIO_16 or RGMII_TX_CTL. That's the reason for this design.

If 3V3 RMII is used in the application, it is better to assign GPIO_16 as its 50MHz reference clock input to save the signal level shifter. Anyhow, if RGMII shall be used instead, level shifter should be applied because the maximum rating of NVCC_RGMII is 2.625V only and it can not be connected to the same 3V3 power source as NVCC_NENT.

My apologies for the inconvenience. I hope this information helps!

Regards,

[ilariogottardel]

Hello Gusarambula,

So, even using GPIO_16 for RMII, one would need a level shifter for sourcing the clock in RGMII mode anyway, is this correct?

Thank you very much