i.MX6DL: Why MMDC_CH1 handshake can be bypassed when enter low power mode

[mmj]

Before entering low power mode, CCM_CLPCR bit 21 (bypass_mmdc_ch1_lpm_hs) is set to bypass MMDC_CH1 handshake. The code can be found in function imx6_set_lpm() at file arch/arm/mach-imx/pm-imx6.c in imx_3.10.53_1.1.0_ga release. I have 2 questions here:

1. Why MMDC_CH1 handshake can be bypassed when entering low power mode and don't wait for MMDC_CH1 handshake?

2. Why we didn't bypass MMDC_CH0 handshake in the same code as well?

Thanks for your kind attention.

[Yuri]

Hello,

MMDC_CH1 is used for two-channel mode with LPDDR2.

Have a great day,
Yuri

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[mmj]

Hello Yuri,

Yes, I know MMDC_CH1 is used in two-channel mode. 

For i.MX6DQ, i.MX6_set_lpm() just bypass the MMDC_CH1 handshake only. Why it don't bypass MMDC_CH0 handshake as well or wait for both MMDC_CH0 & MMDC_CH1 handshakes? This is something I don't understand. 

Thanks.

[Yuri]

Hello,

 For  two-channel mode with LPDDR2, it is needed to control both 

MMDC_CH0 & MMDC_CH1. For SDP / SDB designs MMDC_CH0

controls all memory. 

Regards,

Yuri.

[mmj]

Hello Yuri,

The field definitions of CCM_CLPCR is

Field	Description
21 bypass_mmdc_ch1_lpm_hs	Bypass handshake with mmdc_ch1 on next entrance to low power mode (STOP or WAIT). CCM doesn't wait for the module's acknowledge. 0     Handshake with mmdc_ch0 on next entrance to low power mode will be performed. 1     Handshake with mmdc_ch0 on next entrance to low power mode will be bypassed.
19 bypass_mmdc_ch0_lpm_hs	Bypass handshake with mmdc_ch0 on next entrance to low power mode (STOP or WAIT). CCM doesn't wait for the module's acknowledge. 0     Handshake with mmdc_ch0 on next entrance to low power mode will be performed. 1     Handshake with mmdc_ch0 on next entrance to low power mode will be bypassed.

Thus when the "bypass_mmdc_chX_lpm_hs" bit is set, that MMDC channel will be bypassed on next entrance to low power mode.

Now in BSP,

1) For single core device such as i.MX6SL/i.MX6SX, "bypass_mmdc_ch0_lpm_hs" is set and thus MMDC_CH0 is bypassed when enter low power mode. Why it is necessary to bypass the MMDC_CH0 handshake? (I suppose it needs to complete all DRAM transactions and should wait for the MMDC_CH0 handshake, hence should set to 0).

2) For multi core device such as i.MX6D/Q, "bypass_mmdc_ch1_lpm_hs" is set and thus MMDC_CH1 is bypassed when enter low power mode. Why MMDC_CH0 handshake is don't care for multi core?

Thanks.