i.MX6DL - Flexcan Transmission Interrupt random delay

adrien_sierra · ‎10-22-2020

Hello,

I'm using i.MX6DL processor with QNX RTOS. I've develop the Flexcan driver by myself. Everything seems to work correctly but I'm experiencing some performance problem.

In my system, I have to send each 5ms a CAN frame. The frame has the corresponding IMASK set to generate an interruption when transmission is done.

Most of the time, this transmission sequence is working well :

1. Application send data to driver

2. Driver checks if respective interruption bit is set and clear it

3. Driver checks if MB is Inactive

4. Driver writes id,data,dlc,CS word

5. MB is activated, CAN frame is transmitted

6. Interruption 0x8E (IRQ 142 - FLEXCAN1) is fired, driver catch it and handle it

7. Driver answers to application to say it's OK you can continue, frame is sent.

This transmission sequence is during around 200-300 microseconds. But randomly like 5 minutes after starting the application, it's taking 4-5ms...

After a lot of verification, it seems that the interruption is fired with a 4ms delay instead of 200us and I don't understand why ? Am I missing something here ? Is there a mecanism to add in order to protect the MB, for example check ESR1[TX] register to be sure transmission is finished ?

The question is why the interruption delay since activation of MB is taking randomly milliseconds instead of microseconds ?

If you have ideas, it will be a great help for me.

Thank you.

adrien_sierra · ‎10-28-2020

Hi igor,

I've check another point and it seems to work. I've check "Chip Errata for the i.MX 6Solo/6DualLite" rev6 and there is a chapter for Flexcan concerning a bug for transmission.

I've patch my code by adding three things inspired from chip errata document :

1) Start using Mailbox from index 1 and not 0. MB1...MX63

2) Write INACTIVE code to current mailbox for transmission before activation

3) Write INACTIVE code twice to MB0 just after activation of current mailbox for transmission

The system is now running since 3 hours and I still don't have an error. Let's wait at least 10 hours.

I hope it will be fixed.

Anyway, thanks for help Igor !

在原帖中查看解决方案

igorpadykov · ‎10-22-2020

Hi adrien_sierra

random interruption delay may happen due to high internal bus load

produced by some masters, described in Chapter 46
Network Interconnect Bus System (NIC-301)

i.MX 6Solo/6DualLite Applications Processor Reference Manual

Just for test one can try to disable them (or set lower priority) one by one.

Best regards
igor

adrien_sierra · ‎10-23-2020

Hi igorpadykov,

Thank you for your answer but I'm totally new with what you are suggesting (NIC-301). I've check SDLRM chapter 46 but I don't understand what I'm supposed to do when you say "disable them" or "set lower priority". I've download also "AMBA® Network Interconnect (NIC-301) Technical
Reference Manual, version r2p3".

I can do a memory mapping via GPV port and access a master but then I don't see an interface register to manage priority or enable/disable state ?

Best regards,

igorpadykov · ‎10-23-2020