I have the same problem!
linux 4.9.14
DMA is disabled.
UART speed 307200, 8n2.
The imx6 receive 10 zero bits and fixes the FRAME error.
Next, the imx6 receive a short start bit (1.2 usec) and goes nuts.
The processor starts to accept infinitely 0xFF.
Helps only software reset uart.
URXD0 = 80B9
URXD0 = D000 - FRAME error
URXD0 = 80FF
URXD0 = 80FF
URXD0 = 80FF
...
URXD0 = 80FF
Photo of oscillograph.
If the processor receives the normal start bit (3.2 usec), then there is no problem.
URXD0 = 8007
URXD0 = D000 - FRAME error
URXD0 = 80FF
Photo of oscillograph.
//---------------------------
Path imx.c:
if (unlikely(rx & URXD_ERR)) {
+ if (rx & (URXD_BRK | URXD_FRMERR))
+ imx_software_reset(sport);
if (rx & URXD_BRK)
+static void imx_software_reset(struct imx_port *sport)
+{
+ unsigned long temp;
+ int ubir, ubmr, uts;
+
+ ubir = readl(sport->port.membase + UBIR);
+ ubmr = readl(sport->port.membase + UBMR);
+ uts = readl(sport->port.membase + IMX21_UTS);
+
+ // Clear the SRST_B bit (UCR2[0])
+ temp = readl(sport->port.membase + UCR2);
+ temp &= ~UCR2_SRST;
+ writel(temp, sport->port.membase + UCR2);
+
+ // Wait for software reset complete: poll SOFTRST bit (UTS[0]) until it is 0.
+ while (!(readl(sport->port.membase + UCR2) & UCR2_SRST))
+ barrier();
+
+ // Re-program baud rate registers: Re-write UBIR and UBMR.
+ writel(ubir, sport->port.membase + UBIR);
+ writel(ubmr, sport->port.membase + UBMR);
+ writel(uts, sport->port.membase + IMX21_UTS);
+}
