i.MX6 DDR3 seemingly unresponsive. Length tuning?

[jaydcarlson]

I'm in the process of bringing up a custom i.MX6 board (based heavily on the RIoTBoard). I deploy U-Boot into RAM using the USB bootloader, then attach my JLink to the board and start debugging, but as soon as it jumps into RAM memory space, all the addresses read as the same, gibberish value, leading me to conclude something screwy is going on with my DDR. I'm going to lower the clock rate, but right now, I'm trying to figure out if there's an electrical connectivity problem or a trace length tuning problem. Here are the lengths of my T-topology between the i.MX6 and the two DRAM chips:

DRAM_BANK0: 860-873 mil  (+/- 6.5 mil)

DRAM_BANK1: 740-764 mil  (+/- 12 mil)

DRAM_BANK2: 798-821 mil  (+/- 11.5 mil)

DRAM_BANK3: 818-844 mil  (+/- 13 mil)

ADDR/CMD/CTRL: 1614-1658 mil (+/- 22mil)

CLK0: 1665/1678 mil (+/- 6.5 mil)

CLK1: 1619/1632 mil (+/- 6.5mil)

As you can see, all the single-ended lines are within the standard +/- 25mil spec. The differential clocks are a little off (+/-5 mil is what I’ve always heard for clocks), but they should be alright.

The biggest layout problem I can see is that CLK1 is a little shorter than I would have liked. It should be at least 1658 mil, as that’s the longest ADDR/CMD/CTRL line, but it’s a little shorter than that. It’s only off by 40 mil (on the order of 5-10 picoseconds), which seems close enough? Maybe not, though?

If the CLK trace is too short, would this manifest as catastrophic failure of the memory?

I couldn't get a thin enough stack-up to hit 50-ohm impedance -- I'm stuck at closer to 65 ohm. Is that going to be problematic? I wouldn't think so given the short signal traces.

The only other differences I see between my board and the RIoTBoard are:

• I’m using 768-ohm resistors to build the DDR_VREF divider – RioTBoard uses 240-ohm resistors.
• Slight differences in decoupling capacitors all over the place – I'm using 220 nF for everything, while the RIoTBoard has some 100nF and some 220nF spec'd.
• The RioTBoard has a 4.7 uF cap on VREF – I don't have any large cap on it. I rely on the dual 220 nF decoupling caps on each VREF rail.
• RioTBoard specs the MT41K256M16HA-125:E part, but we’re using the industrial version (MT41K256M16HA-125 IT:E) for wider operating temperature.

Any ideas?

[art]

Both signal trace length match issue and impedance mismatch can fatally affect the DDR3 interface. First, keep the clock signal the longest one among all other (even by adding some laps to it). Second, keep the traces impedance as close to 50Ohm as possible (e.g. by varying the trace width). Also, try to play with the DDR3 signal strength settings in the processor.

For more information on the DDR3 interface PCB layout rules and tricks, refer to the Sections 3.1 to 3.6 of the i.MX6 Series Hardware Development Guide Rev.1 document, available on the Freescale web site (check the "User Guides" section):

http://www.freescale.com/products/arm-processors/i.mx-applications-processors-based-on-arm-cores/i.m...

Have a great day,
Artur

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------