We have a setup on i.MX 8QuadMax Multisensory Enablement Kit where:
We are running a hypervisor software at EL2 (DDR address 0xE0000000-0xE3000000). The memory area is mapped as: Outer Shareable, Inner Write-Back, Outer Write-Back Normal memory with Read allocation hints and Write allocation hints and not transient.
We noticed that our spinlock implementation which works on other armv8 SoCs does not work if we have enabled both the a53 set of cores and a72 set of cores. As exclusive access we use LDXR & STXR instructions. We use system wide data memory barrier (dmb sy) after storing the spinlock value. Spinlock variable is stored at address 0xE0016000 in data section (and is 64bits wide).
a72 core does not seem to "see" if a53 core has acquired the spinlock (or vice versa). We are not sure whether this is because of exclusive monitor, cache coherency between the clusters or some other cause. When stepping the spinlock code with debugger the LDRX & STXR seem to work as expected. We store the MPIDR_EL1 to the spinlock variable and can in this way see that when the issue happens (i.e. cores accessing the data protected with spinlock simultaneously) that it is always a53 and a72 core accessing the shared data at the same time. And the ownership of the spinlock is one of those two cores.
But for example if we run the same code on the same hardware with the same configuration - but we only use a53 cores - the spinlock implementation works as expected.
Is this expected behavior? And if it is expected: is there a solution or workaround for this (other than running only on one cluster of cores)?
