a bsp beginner's questions for imx8mq ethernet device-tree

[lsahn]

Hello!

Recently I started BSP works as a beginner at the office and things are I don't fully understand why its dts described as...

I know why clocks are needs, but those definitions of clock related properties are clueless...

1. "clocks" part, why and what's the purpose of these items?

2. "clock-names" part, what are ipg ahb and so forth...

3. "assigned-clocks" parts, are totally out of knowledge...

I really appreciate that if you guys explain about that, or get me some references to understand them.

Thank you!

[Zhiming_Liu · Accepted solution]

Hi @lsahn 

Please open i.MX8MQ reference manual and source code.

IMX8MQ_CLK_ENET1_ROOT name is "ipg", fec driver will call devm_clk_get to get this clock id in clock framework and enable this clock.

fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
ret = clk_prepare_enable(fep->clk_ipg);

IMX8MQ_CLK_ENET1_ROOT is index value in hws, this is a gate to control open/close.

hws[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_hw_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);

Then we assign IMX8MQ_CLK_ENET_AXI clock to this index value.IMX8MQ_CLK_ENET_AXI is real clock that we may need modify it's speed  in hardware.

hws[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mq_enet_axi_sels, base + 0x8880);

 The we need choose parent clock about this clock, why? There are lots of source clocks that we can choose to generate this AXI_CLK 

Here we choose IMX8MQ_SYS1_PLL_266M which is SYSTEM_PLL1_DIV3, we can see the parms about imx_clk_hw_fixed_factor.

hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3)

[lsahn]

Thank you so much!