Why IMX8MQ_VIDEO_PLL1 frequencies has been fixed to 59999999 ?

[giuseppepagano1]

Hi,

we are having a big issue in driving a Full-HD LVDS display on a custom board based on i.MX8MQ.

Display is connected to mipi-dsi bus through a MIPI-DSI to LVDS bridge from TI.

It was very difficult for us to find a working setup, because apparently MIPI-DSI controller of i.mx8mq produces a non regular data flow, so horizontal LVDS timeline from the bridge was not stable (this situation was acceptable from lots of display, but not from the display panel we was working on ..).

Finally we find the solution:

to mantain image syncronization on LVDS display we have to change "IMX8MQ_VIDEO_PLL1" frequencies from 599999999 to 600000000. We know this can't be the definitive configuration, but the question is:  Why IMX8MQ_VIDEO_PLL1 was fixed to 599999999 values ? There is some limit on that clock, so it can't exceeded 60 MHz ?

Thanks for the help.

Regards

Giuseppe

[giuseppepagano1]

Hi, just to clarify.

I was referring to patches I've seen on the web.  For example here:

  dt-bindings: imx: Add binding for IMX NWL mipi dsi host controller (d16173fd) · Commits · Guido Günt... 

IMX8MQ_VIDEO_PLL1 parent is 25MHz, but clock frequencies still 599999999

Moreover maybe there is an error in codeaurora  root/drivers/clk/imx/clk-imx8mq.c file (branch imx_4.14.98_2.0.0_ga)

/* config video_pll1 clock */

clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_REF_SEL], clks[IMX8MQ_CLK_27M]); clk_set_rate(clks[IMX8MQ_VIDEO_PLL1], 593999999);

Thanks for your responce,

Best Regards

Giuseppe

[igorpadykov]

Hi Giuseppe

>There is some limit on that clock, so it can't exceeded 60 MHz ?

there is no limit on it but since VIDEO PLL1 is using 27MHz reference clock, 600MHz

(600000000) can not be derived exactly: 600MHz/27MHz = 22,22222(2)  [all "2"] and

since fractional divider PLL_FRAC_DIV_CTL (divider values are 1 to 2^24) has limited accuracy

24 bit, 22.2222222 * 27 = 599999999.

Description can be found in sect.5.1.8.6 VIDEO PLL Configuration 1 Register (CCM_ANALOG_VIDEO_PLL1_CFG1) i.MX8MQ Reference Manual

https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf 

Best regards
igor
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