Hello commuity,
I have one question concern with low level boot sequence.
Environment :
- i.MX6DL @800MHz
- DDR3 x 4pcs. (64bit bus)
- SPI-NOR (u-boot and kernel)
- eMMC (RootFS)
When SPI-NOR boot is selected:
i.e. BOOT_MODE[1:0]=Internal Boot, BOOT_CFG1[7:4]=Serial ROM(SPI)
In this case, the system boot up sequence is as following :
A piece of DDR was broken after ESD test, so DDR stress test became fail.
In other word, maybe above process 3, 4 (i.e.Copy and Load the u-boot / jump to DDR address) is not executed.
Best Regards,
Kanou
Solved! Go to Solution.
Hi Kanou
you are right: in this case i.MX6 ROM BIOS will transition to the serial download mode.
Best regards
igor
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Hi Igor,
Thank you for replying.
My customer say:
If possible, Would you tell me how serial download mode is determined by the BIOS.
What kind of logic does it change in a serial downloading mode in?
For example, jump to exception interrupt handler, DDR CRC check error, ....
Best Regards,
kanou
Hi Kanou
yes ROM executes jump to exception interrupt handler.
Best regards
igor
Hi Kanou
you are right: in this case i.MX6 ROM BIOS will transition to the serial download mode.
Best regards
igor
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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