What happens to the boot sequence when CA53 Core0 is software reset?

[Takashi_Kashiwagi]

HI Community.

I read 6.1 System Boot in the IMX8MM reference manual, but I didn't understand the behavior when resetting the software.

I want to use CM4 Core for alive monitoring of CA53.

According to RM, the SRC_A53RCR0 can be used to reset the CA53 core, but I could not understand what the boot sequence would be when the Core0 was software reset.

Is it the same sequence as POR?

（It was useful if there was a boot option that would start from CM4 at POR......）

Best Regards,

T.Kashiwagi

[Takashi_Kashiwagi]

Hi Igor

yes. But there is chance that it will hang, as ROM expects POR reset (so whole processor is ready to boot).

As a reminder, if CM4 resets Core0 with A53_CORE_RESET0, will the CM4 core be affected? ,

Best Regards,

T.Kashiwagi

[igorpadykov]

Hi Kashiwagi

>if CM4 resets Core0 with A53_CORE_RESET0, will the CM4 core be affected? 

no

Best regards
igor

[igorpadykov · Accepted solution]

Hi Kashiwagi

>According to RM, the SRC_A53RCR0 can be used to reset the CA53 core, but I could

>not understand what the boot sequence would be when the Core0 was software reset.

strictly speaking only resetting the CA53 core may not be sufficient for successful boot,

as boot ROM expects that other processor modules were in predefined (reset) state.

Such state is provided only using POR, as described in sect.6.5.4.1.2.1 POR (SRC_POR_B)  

i.MX 8M Mini Applications Processor Reference Manual

>It was useful if there was a boot option that would start from CM4 at POR

sorry this is not possible.

Best regards
igor
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[Takashi_Kashiwagi]

Hi Igor.

Thank you for responding.

strictly speaking only resetting the CA53 core may not be sufficient for successful boot,

as boot ROM expects that other processor modules were in predefined (reset) state.

Such state is provided only using POR, as described in sect.6.5.4.1.2.1 POR (SRC_POR_B)  

It seems that all cores are reset when POR is reset. I don't want to reset the CM4 core.

It is written that A53_CORE_RESET0 of SRC_A53RCR0 register resets only Core0.

If I reset CA0 Core0 from CM4 using this bit, will Core0 start from boot ROM (0x00000000)?

My ideal is as follows.
・ When resetting CA53 Core0, CM4 core does not want to be reset.
・ When I reset the CA53 core from the CM4 core, I want to start the CA53 core with u-boot-spl.bin or u-boot.img loaded.

Best Regards,

T.Kashiwagi

[igorpadykov]

Hi Kashiwagi

>>If I reset CA0 Core0 from CM4 using this bit, will Core0 start from boot ROM (0x00000000)?

yes. But there is chance that it will hang, as ROM expects POR reset (so whole processor is ready to boot).

Best regards
igor