Hello,
I've been encountering trouble due to the WDOG_RESET.
In the datasheet, it says :
34.5.6 Watchdog Reset Control
The WDOG generated reset signal wdog_rst can be asserted by a software write to the Software Reset Signal (SRS) bit of the WCR. It can also be generated by the following event:
• WDOG time-out
The wdog_rst is generated for 0.5 seconds for a time-out, but is deasserted early if a system reset is detected. In case of a software reset, the wdog_rst is asserted after three clocks of resetting the SRS bit and remains asserted for three IPG clocks (IP global functional clock). If a system reset is asserted in between, it deasserts before three IPG clocks have elapsed.
It's only when the "wdog_rst" is deasserted, the system reboots
3.5.2 ARM9 Platform Reset
Any qualified global reset signal resets the ARM9 Platform and all related peripherals to their default state.
After the internal reset is deasserted, the ARM9 processor begins fetching code from the internal bootstrap ROM or CS0 space. The memory location of the fetch depends on the configuration of the BOOT pins and the value of the TEST pin on the rising edge of the HRESET.
My question is : What happens to the system during those 500ms ? Regarding the interrupts processing and threads ?
