Using i.MX6 to generate 125MHz reference clock for RGMII interface

[dank1]

Hello,

I designed a custom board using the i.MX6 (Dual) using the RGMII interface to a Marvell 88E1118R PHY.

I have connected the GPIO16 pin (R2) to the ENET_REF_CLK pin (V22) externally on the PCB and would like to configure the CPU to generate the 125MHz reference clock.

I have read that it is possible:

https://community.freescale.com/message/378081#378081

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf?fasp=1&WT_TYPE=UsersGuides&W...

To summarize what I have understood - in order to achieve this I should:

• Set CCM_ANALOG_PLL_ENETn[1:0] to ‘11’ for 125MHz
• Set IOMUXC_SW_MUX_CTL_PAD_GPIO16 “MUX MODE” to ‘010’ for ENET_REF_CLK alternate function ALT2
• SET IOMUXC_SW_MUX_CTL_PAD_GPIO16 SION bit to ‘1’ – good practice.
• Set IOMUXC_GPR1[21] to ‘1’ in order to get reference clock from ANATOP and output to GPIO16 PAD (R2)
• Set IOMUXC_SW_PAD_CTL_PAD_GPIO16[7:6] "SPEED" to '10' or '11' (MEDIUM/MAXIMUM)
• Set IOMUXC_SW_PAD_CTL_PAD_GPIO16[0] "SRE" to '1' (FAST Slew Rate)

Are my understandings correct?

Did I miss anything?

What should I set IOMUXC_ENET_REF_CLK_SELECT_INPUT to? Does it matter in the case of RGMII?

[Yuri]

"i.mx6 requires a Reference clock externally on ENET_REF_CLK pad and without

that it could not work / generate the TX CLK."

Please refer to the following :using GPIO_16 pin as reference clock in RGMII

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[dank1]

I am creating a 125MHz clock as defined in the design Guide (chapter 12) and connecting it externally to the ENET_REF_CLK pad (V22).

What is wrong with that?

[Yuri]

  As I understand You are trying to use the GPIO_16 as clock source :  assuming the internal source
is routed externally from GPIO_16 to ENET_REF_CLK for RGMII, but till now such configuration
has not been tested / validated. As I know  there are plans to validate the internal clk source for ref clk,
but this a longer term investigation. 

~Yuri.

[dank1]

Yes,

I have a board where the GPIO16 is externally connected to ENET_REF_CLK (as was suggested by Freescale to me during the board design stage).

Before changed the board (respin - layout) I want to check my RGMII connection.

Are the steps I indicated above enough to output the 125MHz clock as reference clock. I know this is not supported/validated.

What are the specifications of the needed 125MHz reference clock for the RGMII (Jitter, etc...)? I cannot find them in the documentation.

[Yuri]

  In addition to software settings above, it is needed to configure register
IOMUXC_ENET_REF_CLK_SELECT_INPUT for mode ALT2.
(NOTE: Pad GPIO_16 is involved in Daisy Chain).

Next, below are some recommendations from internal discussions “how to optimize the set up for success :

[assuming GPIO_16 is contact R2 and ENET_REF_CLK is contact V22]
 

1a. Do not hang any other loads, etc on this signal. In our case, R2 directly fed V22 with no other

loads, test points, etc. The only component involved was a 0201 zero ohm option resistor mounted

very close to the processor.

1b. Check if logic level conversion is needed. To optimize this approach, the component

choices and layout should minimize parasitic capacitance. Place the circuit very close to the associated

processor contacts. Use 0201 (preferred) or 0402. Simulation is needed.

2. The ref clk PCB routing should be as short as possible, with minimum number of vias.

3. In our case, associated power rails NVCC_GPIO and NVCC_ENET were very well decoupled and tied to power/GND planes. Noise on these particular power rails (in our case) couple into ref clk.

4. Per our previous communication, customers must validate their approach by running their system software. Some software generates more system noise than other software.

5. Don't locate ref clk traces/level converters near noise-radiating traces/signals.

6. Turn off hysteresis and turn off PU/PD on ref clk input.

7. Examine ref clk with active probe/scope at the ref clk input. Try different drive strengths on the output to optimize.

8. Include oscillator module as a system option for backup."

~Yuri.

[dank1]

So I asked my SW guy to enter the following configuration (you can see the readback results for the appropriate addresses after boot):

• Set CCM_ANALOG_PLL_ENETn[1:0] = ‘11’ (DIV_SELECT = 125MHz).    0x20C80E0: 0x00011003

• Set IOMUXC_SW_MUX_CTL_PAD_GPIO16[2:0] = ‘010’ (MUX MODE = ALT2 - Select signal ENET_REF_CLK).   0x20E0248: 0x00000012
• Set IOMUXC_SW_MUX_CTL_PAD_GPIO16[4] = ‘1’ (SION – ENABLED).   0x20E0248: 0x00000012

• Set IOMUXC_GPR1[21] = ‘1’ (To get reference clock from ANATOP and output to GPIO16 PAD R2)   0x20E0004: 0x48600005

• Set IOMUXC_SW_PAD_CTL_PAD_GPIO16[12] = ‘0’ (Pull/Keep = DISABLED)   0x20E0618: 0x0001B0D9
• Set IOMUXC_SW_PAD_CTL_PAD_GPIO16[7:6] = ‘11’ (SPEED = MAXIMUM)    0x20E0618: 0x0001B0D9
• Set IOMUXC_SW_PAD_CTL_PAD_GPIO16[5:3] = ‘011’ (Drive Strength = 50 Ohm @3.3V)    0x20E0618: 0x0001B0D9
• Set IOMUXC_SW_PAD_CTL_PAD_GPIO16[0] "SRE" to '1' (FAST Slew Rate)    0x20E0618: 0x0001B0D9

• Set IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK[16] = ‘0’  (Hysteresis = DISABLED)    0x20E04E8: 0x0000B0F1
• Set IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK[12] = ‘0’  (Pull/Keep = DISABLED)    0x20E04E8: 0x0000B0F1
• Set IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK 16[7:6] = ‘11’ (SPEED = MAXIMUM)    0x20E04E8: 0x0000B0F1
• Set IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK [0] "SRE" to '1' (FAST Slew Rate)    0x20E04E8: 0x0000B0F1

• Set IOMUXC_ENET_REF_CLK_SELECT_INPUT[0] to ‘1’ (GPIO16_ALT2)    0x20E083C: 0x00000001

I do not get any sort of clk/oscilating on the signal.

I am measuring (scope) the voltage on the R2-V22 external connection:

• When the board is not programmed yet I get '1' (3.3V) on the pins.
• When the SW loads I see the pins drop to '0' (0v).

Can you please review the assignments again and see if I have it wrong or something is missing.

In particular those for IOMUXC_SW_PAD_CTL_PAD_GPIO16 and IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK.

Thank you

[Yuri · Accepted solution]

As for CCM_ANALOG_PLL_ENETn, please try the next configuration  :
1) clear bit 16, BYPASS ;
2) set bit 13, ENABLE ;

3) clear bit 12, POWERDOWN.

~Yuri.

[dank1]

Now I get the desired 125MHz clock.

Thank you.