Unknown pad configuration in SABRESD board devicetree

[nexy_sm]

Hi all guys,

I am inspecting the device tree of the sabresd board (imx6qdl-sabresd.dts). Particurarly part:

fsl,pins = <
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
>;
};

I do not understand why 0x80000000, because those registers have only lower two bytes with meaningful information. This however raises the following question to me:

What is the meaning of the drive strength in this case. Imagine that we write all 0s inside the lower two byte of the pad ctl register. If the user changes the direction of the pin, there will be no impact on the pad, cause it is in HiZ?

Thanks

[nexy_sm]

Hi Igor,

thank you for your answer. Could you please tell what is the benefit of using this option? I see that two of those pins are particularly for gpio_keys, which makes me think that for some kind of generic input pin one should use 1<<31 option. Is this correct what I think? My second question would b, if I set drive strength to HiZ, what happens when user change direction of th pin? In my opinion this pin should never be able to drive anything because of high impedance.

[igorpadykov]

Hi Nemanja

benefit is that pad settings are derived from uboot.

What do you mean saying "set drive strength to HiZ",

i.MX6Q pads has not "HiZ" state, only open drain.

Best regards
igor

[nexy_sm]

In IOMUXC PAD_CTL registers there is a Drive Strength Field (bits 5-3) which in my opinion should be a resistor in series with the output.

[igorpadykov]

this does not enable "HiZ", may be useful to check AN5078

Influence of Pin Setting on System  Function and Performance

https://www.nxp.com/docs/en/application-note/AN5078.pdf 

[nexy_sm]

In the document, section 7.1:

The drive strength enable (DSE) can be explained as series resistance between anideal driver’s output and its load. To achieve maximal transferred power, the impedance of the driver has to match the load

impedance.

And the table below showing some resistance values which are not identicla with the values from the reference manual. The application note doesnt say anything about value 000, which is HiZ. This would be nice to test what is it about.

[igorpadykov · Accepted solution]

i.MX6Q pads have not "HiZ" state, only open drain. DSE options are described in

sect.4.8.1 GPIO Output Buffer Impedance i.MX6DQ Datasheet

http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf