Uboot printing garbage after relocates itself to RAM.

[adrian_dusinski]

We have two custom boards and use single memory 4Gb.

On first board, DDR calibration/stress test passed and uboot log normally.

On second board, calibration and stress test passed, u boot logs correct until relocation to RAM memory occurs.

We checked PCB few times but we can't find issues.

I'm uploading DDR configuration and uboot via JTAG.

Log from working board:

U-Boot 2013.04-rc1 (Jun 09 2022 - 14:18:01)

CPU: Freescale i.MX6DL rev1.2 at 792 MHz
Reset cause: POR
Board: I.MX6DL
I2C: ready
DRAM: 0 Bytes
MMC: FSL_SDHC: 0
Card did not respond to voltage select!
MMC init failed
Using default environment

In: serial
Out: serial
Err: serial

Log from broken board:

U-Boot 2013.04-rc1-Imx6dl (Jun 09 2022 - 14:18:01)

CPU: Freescale i.MX6DL rev1.2 at 792 MHz
Reset cause: unknown reset
Board: Imx6dl
I2C: ready
DRAM: 0 Bytes
MMC: FSL_SDHC: 0---------------------------- ! !
f!Tesu St`tts

-------------- ! !
f!Tesu St`tts
C`re die nou rerpond to vnltafe!seldct!
MMC init failed
Using default environment

In: serial
----ov/
-------------- ! !
f!Tesu St`tts
Out: serial
----ov/
-------------- ! !
f!Tesu St`tts
Err: serial

-------------- ! !
f!Tesu St`tts

When uboot use puts function that send data directly to uart, text is okay but if I'm using printf function, text are broken.

Logs from NXP DDR Test tool from broken board:

MMDC0 MPWRDLCTL = 0x40402C32MMDC

registers updated from calibration

Write leveling calibration
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00190019
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00010001

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x417C0178
MPDGCTRL1 PHY0 (0x021b0840) = 0x00000000

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x40405250

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x40402C32

Success: DDR calibration completed!!!

DDR Freq: 297 MHz
t0.1: data is addr test
t0: memcpy11 SSN test
t1: memcpy8 SSN test
t2: byte-wise SSN test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

Success: DDR Stress test completed!!!

I know that problem can be in many place but if I can read memory via JTAG it excludes wrong memory connection?

[adrian_dusinski]

We found out that on new board issues disappear if we enable L1 cache.