The register of RST_to_CKE of MMDC_MDOR

[ko-hey]

Hi all

I want to know the time until DRAM_RESET goes high and CKE goes high.

I'm using i.MX6UL and DDR3.

Q1.

User can change the value to set by [5: 0] RST_to_CKE of MMDC_MDOR register.

Am I correct ?

Q2.

I set the value to 0x23 but the measured value is 424ns.

I understand that the time change by the parameter but I can't understand how to calculate.

Could you tell me how to calculate ?

I referred the following thread.

So if I need make case, please tell me.

https://community.nxp.com/message/964952

Ko-hey

[Yuri · Accepted solution]

Hello,

  Customers can  modify bit field [5: 0] RST_to_CKE of MMDC_MDOR register.  

  We recommend customers using a 32 K  XTAL that has a short start up time, which ensures

that the MMDC initialization is using the 32 KHz XTAL as a reference, instead of the PVT dependent

inaccurate internal osc.

  If internal osc is applied in the case, it may be recommended using the Max value in the MDOR - RST_TO_CKE

to ensure that they always are above the 500us spec.This may result in some processors being delayed a little

longer than necessary, but will meet JEDEC specifications.

Have a great day,
Yuri

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[ko-hey]

Hi Yuri Muhin

Thank you for reply.

I have another question.

Q1.

According to your answer, there is a case different from register setting value.

The cause is mainly PVT and 32KHz XTAL accuracy.

Am I correct ?

Q2.

> If internal osc is applied in the case, it may be recommended using the Max value in the MDOR - RST_TO_CKE to ensure that they always are above the 500us spec.

How to ensure the spec ?

Ensuring by register ?

Ko-hey

[Yuri]

Hello,

 1.

    Correct, PVT and 32KHz XTAL accuracy influences on the timings.

2.

  500us is minimal value,   Max value in the MDOR - RST_TO_CKE should provide 

greater time value. 

Regards,

Yuri.