Hello,
we are currently planning a real time application which should executed on the Cortex-M4 of the i.MX8 platform during a performance intensive application is running on the Cortex-A35.
The Cortex-M4 application communicates with SPI/I2C hardware interface
The Cortex-A35 application displays information on the GUI
Therefore we have compared the following i.MX8 platform datasheets:
- IMX8MPRM (Rev. 1, 06/2021)
- IMX8DQXPRM (Rev. 0, 05/2020)
After comparing the system block diagram between the IMX8MPRM and IMX8DQXPRM platforms,
the following questions have arisen:
- Do both SoCs use the same bus system architecture?
- The IMX8MPRM manual describes an AXI and AHB Switch Fabric
- The IMX8DQXPRM manual just mension a SSI (Source Synchronous Interface)-Interface between the subsystems on the platform
- What is the difference between SSI system bus and the AXI and AHB Switch Fabric?
- All communications to subsystems such as offchip memory or SPI run via the system bus (the bottleneck).
- Is it still possible to access the SPI/I2C by the Cortex-M4 in hard real time via the system bus?
- Is there already a newer revision of the i.MX8X platform manual IMX8DQXPRM?
Thank you for your answer in advance.
Best regards,
David
IMX8DQXPRM Block Diagram:
IMX8MPRM Block Diagram:
1 解答
